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Fri, 6 Dec 2024 01:36:00 GMT Received: from yijiyang-gv.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 5 Dec 2024 17:35:56 -0800 From: Yijie Yang Date: Fri, 6 Dec 2024 09:35:04 +0800 Subject: [PATCH v5 1/2] arm64: dts: qcom: qcs8300: add the first 2.5G ethernet Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241206-dts_qcs8300-v5-1-422e4fda292d@quicinc.com> References: <20241206-dts_qcs8300-v5-0-422e4fda292d@quicinc.com> In-Reply-To: <20241206-dts_qcs8300-v5-0-422e4fda292d@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran CC: , , , , Yijie Yang , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1733448951; l=2280; i=quic_yijiyang@quicinc.com; s=20240408; h=from:subject:message-id; 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Add the internal SGMII/SerDes PHY node as well. Reviewed-by: Konrad Dybcio Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 43 +++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi index 2c35f96c3f289d5e2e57e0e30ef5e17cd1286188..4e37a3ed29f302192dfb37e1489ec325c84d6ea8 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -772,6 +772,15 @@ lpass_ag_noc: interconnect@3c40000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + serdes0: phy@8909000 { + compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; + reg = <0x0 0x08909000 0x0 0x00000e10>; + clocks = <&gcc GCC_SGMI_CLKREF_EN>; + clock-names = "sgmi_ref"; + #phy-cells = <0>; + status = "disabled"; + }; + pmu@9091000 { compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg = <0x0 0x9091000 0x0 0x1000>; @@ -1308,6 +1317,40 @@ IPCC_MPROC_SIGNAL_GLINK_QMP }; }; + ethernet0: ethernet@23040000 { + compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; + reg = <0x0 0x23040000 0x0 0x00010000>, + <0x0 0x23056000 0x0 0x00000100>; + reg-names = "stmmaceth", "rgmii"; + + interrupts = , + ; + interrupt-names = "macirq", "sfty"; + + clocks = <&gcc GCC_EMAC0_AXI_CLK>, + <&gcc GCC_EMAC0_SLV_AHB_CLK>, + <&gcc GCC_EMAC0_PTP_CLK>, + <&gcc GCC_EMAC0_PHY_AUX_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "phyaux"; + power-domains = <&gcc GCC_EMAC0_GDSC>; + + phys = <&serdes0>; + phy-names = "serdes"; + + iommus = <&apps_smmu 0x120 0xf>; + dma-coherent; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <20480>; + + status = "disabled"; + }; + nspa_noc: interconnect@260c0000 { compatible = "qcom,qcs8300-nspa-noc"; reg = <0x0 0x260c0000 0x0 0x16080>;