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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Geert Uytterhoeven Cc: netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Dege , Christian Mardmoeller , Dennis Ostermann , Nikita Yushchenko Subject: [PATCH net-next 2/4] net: renesas: rswitch: align mdio C45 operations with datasheet Date: Sun, 8 Dec 2024 20:52:34 +0500 Message-Id: <20241208155236.108582-3-nikita.yoush@cogentembedded.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20241208155236.108582-1-nikita.yoush@cogentembedded.com> References: <20241208155236.108582-1-nikita.yoush@cogentembedded.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Per rswitch datasheet, software can know that mdio operation completed either by polling MPSM.PSME bit, or via interrupt. Instead, the driver currently polls for interrupt status bit. Although this still provides correct result, it requires additional register operations to clean the interrupt status bits, and generally looks wrong. Fix it to poll MPSM.PSME bit, as the datasheet suggests. Signed-off-by: Nikita Yushchenko --- drivers/net/ethernet/renesas/rswitch.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/renesas/rswitch.c b/drivers/net/ethernet/renesas/rswitch.c index 57d0f992f9a5..120d56754692 100644 --- a/drivers/net/ethernet/renesas/rswitch.c +++ b/drivers/net/ethernet/renesas/rswitch.c @@ -1177,32 +1177,26 @@ static int rswitch_etha_set_access(struct rswitch_etha *etha, bool read, if (devad == 0xffffffff) return -ENODEV; - writel(MMIS1_CLEAR_FLAGS, etha->addr + MMIS1); - val = MPSM_PSME | MPSM_MFF_C45; iowrite32((regad << 16) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); - ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); + ret = rswitch_reg_wait(etha->addr, MPSM, MPSM_PSME, 0); if (ret) return ret; - rswitch_modify(etha->addr, MMIS1, MMIS1_PAACS, MMIS1_PAACS); - if (read) { writel((pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); - ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); + ret = rswitch_reg_wait(etha->addr, MPSM, MPSM_PSME, 0); if (ret) return ret; ret = (ioread32(etha->addr + MPSM) & MPSM_PRD_MASK) >> 16; - - rswitch_modify(etha->addr, MMIS1, MMIS1_PRACS, MMIS1_PRACS); } else { iowrite32((data << 16) | (pop << 13) | (devad << 8) | (phyad << 3) | val, etha->addr + MPSM); - ret = rswitch_reg_wait(etha->addr, MMIS1, MMIS1_PWACS, MMIS1_PWACS); + ret = rswitch_reg_wait(etha->addr, MPSM, MPSM_PSME, 0); } return ret;