From patchwork Fri Dec 13 13:41:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13907025 X-Patchwork-Delegate: kuba@kernel.org Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B69671E048A; Fri, 13 Dec 2024 13:41:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734097311; cv=none; b=PjYAjz4ew2K7pS/Olox0c4iPrjpXFEgVhxsN82KHta1u5Ndu6ORvhUmu6wfbBTCt6mT4r0ze69lbi0tiI7n+ZmK+vXRGOwN2JqLfTouECH+mrUT1RPf4Or9fQnTUy2c+k+HQKqmWfRZDQ7RV/0PRLkipS2a9p4uU8jlFCBYM+2g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734097311; c=relaxed/simple; bh=e2K9xQ3ZvYEJWrTowWR9ILxUeHoj5YBQVIgtoHUtVjk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=eovi1/oYYnN5nwdb4BqnJkK2MAysSwMwWvKw6pFvyqUuK741DZCD2/o6ex2Xq9bbxtmTdx06S3AFisM2RW5aWFZdi8rR8nbz1ti65sggehqulIGQaSu4lG+ag4osTAgWZCp6jy7aDpbelugjSKpJR4O4Uxk0XCEP/5BfYZKtClM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=qHpRKhAn; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="qHpRKhAn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1734097309; x=1765633309; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=e2K9xQ3ZvYEJWrTowWR9ILxUeHoj5YBQVIgtoHUtVjk=; b=qHpRKhAn6Y1QqzxI90U1xU1q6mS7+U/lBMcJ1jt5epGlGqPJX3u5J25d blKUAvLYWhDchsL18Mk9yzTjkILZwnI7ImHoR3G6v3/dlmtl2nis/byRH gJRRuOm0wc4/KffILNdU708kl1F+EJuVoLXSK5pFs37zzP1weGCW16pnN 8obiqtFf3FMs+GL5sLd97hNGEQa+NeIbEe7QRwHvHSYMyETWLa918RC0Z AtskEEX+mkJr1MAdfrtKN39baKx51d8McpQqzAekEn7oEDpiLh4NWN9o9 hygvuTSEykiw7533p6FUcBv+uHCubijIRkQM+vjui+NI8ocDtyfP5oW1M A==; X-CSE-ConnectionGUID: J8E2tOzOTwasRwDCNa1A1Q== X-CSE-MsgGUID: WEyjgUW9T2y381Bq/3UP+w== X-IronPort-AV: E=Sophos;i="6.12,231,1728975600"; d="scan'208";a="202965479" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 13 Dec 2024 06:41:48 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 13 Dec 2024 06:41:33 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 13 Dec 2024 06:41:29 -0700 From: Daniel Machon Date: Fri, 13 Dec 2024 14:41:04 +0100 Subject: [PATCH net-next v4 5/9] net: sparx5: only return PCS for modes that require it Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241213-sparx5-lan969x-switch-driver-4-v4-5-d1a72c9c4714@microchip.com> References: <20241213-sparx5-lan969x-switch-driver-4-v4-0-d1a72c9c4714@microchip.com> In-Reply-To: <20241213-sparx5-lan969x-switch-driver-4-v4-0-d1a72c9c4714@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , , , , CC: , , , , X-Mailer: b4 0.14-dev X-Patchwork-Delegate: kuba@kernel.org The RGMII ports have no PCS to configure. Make sure we only return the PCS for port modes that require it. Signed-off-by: Daniel Machon Reviewed-by: Russell King (Oracle) --- drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c b/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c index f8562c1a894d..035d2f1bea0d 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c @@ -32,7 +32,19 @@ sparx5_phylink_mac_select_pcs(struct phylink_config *config, { struct sparx5_port *port = netdev_priv(to_net_dev(config->dev)); - return &port->phylink_pcs; + /* Return the PCS for all the modes that require it. */ + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_5GBASER: + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_25GBASER: + return &port->phylink_pcs; + default: + return NULL; + } } static void sparx5_phylink_mac_config(struct phylink_config *config,