@@ -4317,6 +4317,8 @@ static const struct mv88e6xxx_ops mv88e6123_ops = {
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
.pot_clear = mv88e6xxx_g2_pot_clear,
.reset = mv88e6352_g1_reset,
+ .rmu_disable = mv88e6165_g1_rmu_disable,
+ .rmu_enable = mv88e6165_g1_rmu_enable,
.atu_get_hash = mv88e6165_g1_atu_get_hash,
.atu_set_hash = mv88e6165_g1_atu_set_hash,
.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -4467,6 +4469,8 @@ static const struct mv88e6xxx_ops mv88e6161_ops = {
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
.pot_clear = mv88e6xxx_g2_pot_clear,
.reset = mv88e6352_g1_reset,
+ .rmu_disable = mv88e6165_g1_rmu_disable,
+ .rmu_enable = mv88e6165_g1_rmu_enable,
.atu_get_hash = mv88e6165_g1_atu_get_hash,
.atu_set_hash = mv88e6165_g1_atu_set_hash,
.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -4505,6 +4509,8 @@ static const struct mv88e6xxx_ops mv88e6165_ops = {
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
.pot_clear = mv88e6xxx_g2_pot_clear,
.reset = mv88e6352_g1_reset,
+ .rmu_disable = mv88e6165_g1_rmu_disable,
+ .rmu_enable = mv88e6165_g1_rmu_enable,
.atu_get_hash = mv88e6165_g1_atu_get_hash,
.atu_set_hash = mv88e6165_g1_atu_set_hash,
.vtu_getnext = mv88e6352_g1_vtu_getnext,
@@ -555,6 +555,31 @@ int mv88e6085_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port)
MV88E6085_G1_CTL2_RM_ENABLE, val);
}
+int mv88e6165_g1_rmu_disable(struct mv88e6xxx_chip *chip)
+{
+ return mv88e6xxx_g1_ctl2_mask(chip, MV88E6165_G1_CTL2_RMU_MODE_MASK,
+ MV88E6165_G1_CTL2_RMU_DISABLED);
+}
+
+int mv88e6165_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port)
+{
+ int val;
+
+ switch (port) {
+ case 4:
+ val = MV88E6165_G1_CTL2_RMU_MODE_PORT_4;
+ break;
+ case 5:
+ val = MV88E6165_G1_CTL2_RMU_MODE_PORT_5;
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+
+ return mv88e6xxx_g1_ctl2_mask(chip, MV88E6165_G1_CTL2_RMU_MODE_MASK,
+ val);
+}
+
int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
{
return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
@@ -235,6 +235,11 @@
#define MV88E6085_G1_CTL2_DA_CHECK 0x4000
#define MV88E6085_G1_CTL2_P10RM 0x2000
#define MV88E6085_G1_CTL2_RM_ENABLE 0x1000
+#define MV88E6165_G1_CTL2_RMU_MODE_MASK 0x0300
+#define MV88E6165_G1_CTL2_RMU_DISABLED 0x0000
+#define MV88E6165_G1_CTL2_RMU_MODE_PORT_4 0x0100
+#define MV88E6165_G1_CTL2_RMU_MODE_PORT_5 0x0200
+#define MV88E6165_G1_CTL2_RMU_MODE_PORT_RECVD 0x0300
#define MV88E6352_G1_CTL2_DA_CHECK 0x0800
#define MV88E6390_G1_CTL2_RMU_MODE_MASK 0x0700
#define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 0x0000
@@ -317,6 +322,8 @@ int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
int mv88e6085_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port);
+int mv88e6165_g1_rmu_disable(struct mv88e6xxx_chip *chip);
+int mv88e6165_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port);
int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
int mv88e6352_g1_rmu_enable(struct mv88e6xxx_chip *chip, int port);
int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);
The 6165 family allows the use of the RMU on ports 5 and 6. Signed-off-by: Andrew Lunn <andrew@lunn.ch> --- drivers/net/dsa/mv88e6xxx/chip.c | 6 ++++++ drivers/net/dsa/mv88e6xxx/global1.c | 25 +++++++++++++++++++++++++ drivers/net/dsa/mv88e6xxx/global1.h | 7 +++++++ 3 files changed, 38 insertions(+)