| Message ID | 20241216161042.42108-7-alejandro.lucero-palau@amd.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | cxl: add type2 device basic support | expand |
On Mon, 16 Dec 2024 16:10:21 +0000 alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero <alucerop@amd.com> > > Create a new function for a type2 device initialising > cxl_dev_state struct regarding cxl regs setup and mapping. > > Signed-off-by: Alejandro Lucero <alucerop@amd.com> > Reviewed-by: Dave Jiang <dave.jiang@intel.com> > Reviewed-by: Fan Ni <fan.ni@samsung.com> Comments below. J > --- > drivers/cxl/core/pci.c | 47 ++++++++++++++++++++++++++++++++++++++++++ > include/cxl/cxl.h | 2 ++ > 2 files changed, 49 insertions(+) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 3cca3ae438cd..0b578ff14cc3 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -1096,6 +1096,53 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > } > EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); > > +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, > + struct cxl_dev_state *cxlds) > +{ > + struct cxl_register_map map; > + int rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > + cxlds->capabilities); > + /* > + * This call returning a non-zero value is not considered an error since Error code perhaps rather than non-zero value? > + * these regs are not mandatory for Type2. If they do exist then mapping > + * them should not fail. > + */ > + if (rc) > + return 0; > + > + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); > +} > + > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) > +{ > + int rc; > + > + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); > + if (rc) > + return rc; > + > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > + &cxlds->reg_map, cxlds->capabilities); > + if (rc) { > + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); > + return rc; > + } > + > + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) rc is 0. I doubt that's the intent - if it is, return 0; > + return rc; > + > + rc = cxl_map_component_regs(&cxlds->reg_map, > + &cxlds->regs.component, > + BIT(CXL_CM_CAP_CAP_ID_RAS)); > + if (rc) > + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); > + > + return rc; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, "CXL"); > diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h > index 05f06bfd2c29..18fb01adcf19 100644 > --- a/include/cxl/cxl.h > +++ b/include/cxl/cxl.h > @@ -5,6 +5,7 @@ > #define __CXL_H > > #include <linux/ioport.h> > +#include <linux/pci.h> Use a forwards def if all you need is struct pci_dev; > > enum cxl_resource { > CXL_RES_DPA, > @@ -40,4 +41,5 @@ int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, > bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, > unsigned long *expected_caps, > unsigned long *current_caps); > +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); > #endif
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 3cca3ae438cd..0b578ff14cc3 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1096,6 +1096,53 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, } EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, + struct cxl_dev_state *cxlds) +{ + struct cxl_register_map map; + int rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, + cxlds->capabilities); + /* + * This call returning a non-zero value is not considered an error since + * these regs are not mandatory for Type2. If they do exist then mapping + * them should not fail. + */ + if (rc) + return 0; + + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); +} + +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) +{ + int rc; + + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); + if (rc) + return rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, + &cxlds->reg_map, cxlds->capabilities); + if (rc) { + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); + return rc; + } + + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) + return rc; + + rc = cxl_map_component_regs(&cxlds->reg_map, + &cxlds->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS)); + if (rc) + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, "CXL"); + int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) { int speed, bw; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 05f06bfd2c29..18fb01adcf19 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -5,6 +5,7 @@ #define __CXL_H #include <linux/ioport.h> +#include <linux/pci.h> enum cxl_resource { CXL_RES_DPA, @@ -40,4 +41,5 @@ int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, unsigned long *current_caps); +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); #endif