From patchwork Fri Dec 20 13:48:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13916785 X-Patchwork-Delegate: kuba@kernel.org Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94054216E18; Fri, 20 Dec 2024 13:49:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734702577; cv=none; b=lCckE5vQ2XAbo4ixV+qTUnpIqZU9szNJie8yAFFyQG9bsNo+jwktiTrLvFLrrIb2JgC38D5Y5g2VdYHxQwfTb9nu7hxcS0UjZbOJ19oTE8/ZbQbgkaO3PVxIUiaZFJrX2/uzD01bScP9HSp50kJvcPXPSMkyWoybP13XowwEBr4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734702577; c=relaxed/simple; bh=lemXgBt8K5epQpEb61dWKaVFgFUFmL4Rw5o+fkyVr/0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=pRK1JD2W7Z06usn8+NrHCHHypkXBsKOfjJvl9KYXKRucNMTUhlbq2fXs03cmQk1xXxmLd5i1Kpg9k63TmRzhNwLP13CzJY6bAI5mqXLIxOcpRjg+l9BODCX9KkbphyC6ees8rElFKZMaFy1sXzmVQtEmkqmQoZVxLKxxwVy2HwY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=IJ3k9Iy2; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="IJ3k9Iy2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1734702576; x=1766238576; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=lemXgBt8K5epQpEb61dWKaVFgFUFmL4Rw5o+fkyVr/0=; b=IJ3k9Iy2iCv5UmKv/71M5JM6zoTycJTwUN0lwpFAe3+NddHHCOXtZLcB 3csHOEd2Ja58Mq9TmCHuRlyO36WWTj0I0u7Lv9rCDjC1Hb+TzRkntjBYz 69VKl1M+zEd00gF/CWxFRjTZi0Of5/4owoRzpDmbpkJ7/pwMchvnhyS+T ZuOIlHMzwI0z4QOIT62vK59JyGcqS/w07LeoymsWGVlKJaB+B0kqP00ju jIkU9HNLDcq4+LfhifHKNFEYZ1X1uQheP1NVzin18ZVOpClF944Iv4/pF Gx4hmg0xgdaYDHwlcfiT0QoHwgAS0k98zI/4DU5NWG3iLHo62dWTw7K/L g==; X-CSE-ConnectionGUID: mIAoSPyhQLi+IAfuQfXUsw== X-CSE-MsgGUID: NrK3wFoBSpiFGbmNu+VlEg== X-IronPort-AV: E=Sophos;i="6.12,250,1728975600"; d="scan'208";a="267028403" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Dec 2024 06:49:34 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 20 Dec 2024 06:49:11 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 20 Dec 2024 06:49:08 -0700 From: Daniel Machon Date: Fri, 20 Dec 2024 14:48:45 +0100 Subject: [PATCH net-next v5 6/9] net: sparx5: verify RGMII speeds Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241220-sparx5-lan969x-switch-driver-4-v5-6-fa8ba5dff732@microchip.com> References: <20241220-sparx5-lan969x-switch-driver-4-v5-0-fa8ba5dff732@microchip.com> In-Reply-To: <20241220-sparx5-lan969x-switch-driver-4-v5-0-fa8ba5dff732@microchip.com> To: , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Lars Povlsen" , Steen Hegelund , Horatiu Vultur , Russell King , , , , CC: , , , , X-Mailer: b4 0.14-dev X-Patchwork-Delegate: kuba@kernel.org When doing a port config, we verify the port speed against the PHY mode and supported speeds of that PHY mode. Add checks for the four RGMII phy modes: RGMII, RGMII_ID, RGMII_TXID and RGMII_RXID. Reviewed-by: Steen Hegelund Reviewed-by: Horatiu Vultur Tested-by: Robert Marko Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c index 0a1374422ccb..86d6c9e9ec7c 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c @@ -257,6 +257,15 @@ static int sparx5_port_verify_speed(struct sparx5 *sparx5, conf->speed != SPEED_25000)) return sparx5_port_error(port, conf, SPX5_PERR_SPEED); break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_RXID: + if (conf->speed != SPEED_1000 && + conf->speed != SPEED_100 && + conf->speed != SPEED_10) + return sparx5_port_error(port, conf, SPX5_PERR_SPEED); + break; default: return sparx5_port_error(port, conf, SPX5_PERR_IFTYPE); }