Message ID | 20241220-sparx5-lan969x-switch-driver-4-v5-9-fa8ba5dff732@microchip.com (mailing list archive) |
---|---|
State | New |
Delegated to: | Netdev Maintainers |
Headers | show |
Series | net: lan969x: add RGMII support | expand |
On Fri, Dec 20, 2024 at 02:48:48PM +0100, Daniel Machon wrote: > The lan969x switch device supports two RGMII port interfaces that can be > configured for MAC level rx and tx delays. Document two new properties > {rx,tx}-internal-delay-ps in the bindings, used to select these delays. > > Tested-by: Robert Marko <robert.marko@sartura.hr> > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> > Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml index dedfad526666..a73fc5036905 100644 --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml @@ -129,6 +129,24 @@ properties: minimum: 0 maximum: 383 + rx-internal-delay-ps: + description: + RGMII Receive Clock Delay defined in pico seconds, used to select + the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and + 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable + any delay. The Default is no delay. + enum: [0, 1000, 1700, 2000, 2500, 3000, 3300] + default: 0 + + tx-internal-delay-ps: + description: + RGMII Transmit Clock Delay defined in pico seconds, used to select + the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and + 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable + any delay. The Default is no delay. + enum: [0, 1000, 1700, 2000, 2500, 3000, 3300] + default: 0 + required: - reg - phys