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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Shahar Shitrit , Yevgeny Kliteynik , Tariq Toukan Subject: [PATCH net 1/4] net/mlx5: DR, select MSIX vector 0 for completion queue creation Date: Fri, 20 Dec 2024 10:15:02 +0200 Message-ID: <20241220081505.1286093-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241220081505.1286093-1-tariqt@nvidia.com> References: <20241220081505.1286093-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026367:EE_|CH2PR12MB4103:EE_ X-MS-Office365-Filtering-Correlation-Id: 8cffd109-0d92-4297-5c84-08dd20ce8b70 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: P6Q9nkdh7OdNQvZp3IYolQ8xFLZZj6j/nfnq3HaQ9hH1qwrxv1FRD+G2kvHCGe1QvuWmbxk+eNi8ve7efh8rLhEH5WUBYHZiSquLCLsxkmkYR/WoSaS6keBRlP7n80MMUSvba7BD2Xg9uS/dyg2VZ6V8LrkV+NVHlUZzIzhMwFHAs13fXYQpcuedvL/cA/85c0D9C654Lh3i+6HRaO7QGm1mokk31QjNMzL43k27gp0dDGnG89k7lZucp8ENMVYsN1/CtLD6cJTcpBdlfAY8vet/+iMP3dV3TPckP19FyquEsN7wuoCdUP0pJynaWUiM0F6cz9Tv8LpdNlPDv+LXjUxlMBnzOv0ppdmXn0XfHXHMR2jXhvg20TIKI3X+CdSi0xoVH40uJow7HiRcpmSxMDLQyMle8+tMlKQkga30SxNsQmfaWl4c/zLuWnwrrFui8UWMW6TfA42fbavZFmsTmbpS+wbiQxbxJt+nrAN/qXUhTOIBZEOlEWqrdcw3gocICAhQJLqJLJ8ePh9IzHT9YjghwviLwskhCnDld3VYvXNq7f5eXqWb9VMP6z1Np/OxioIkOLxypTX4eODksZLar1Js0JvRqpbiaOgHiiCtgGcsQ+Bsi2yv5KO9Yge87kN4gnJ485HZVD3GaocScBaSTy9sXAzplPclzUCM4GHWjRQcEUaHRMNWphQWxsFU78K7h/SFVtEy4+quDhfwnYO13yUxjs3DeCz+NDBEmuqrTvQkg9Yx77ZL5mmOXShP5EwWssxh8+HO/Orhb83Ek276H4LSADk3rGPAAgWqmaFKQYtBS9lNhVjji9QRLsQwdcnAGRYB8MDNEJ9LaqNVz96GLdm4MyYldbKljqvnRAiN/AXIGou1KQYW6R0I9hPEXFzEKRLVizW9r/SXscq7lY2l1D0hUGy2wiy3OLu8a6USlwu5ZbhSiAbQwu6udr2X1+D/d2taMuWaJgqaWMlF5hp0NZbygwXerOs8Eg9hGGFcPhOWzBwQGmsVrlYHdwNTa95jHLSvMLH7DKFmC6a0MF3wvj+DOWTs6Kb9RwyEG/+iR3W7860CaaET3PYfs/eLMHV670TJLsF9vVL13n93IsxjjFq1ksDYSBUtyeJQkcrSxhCciKLx6/iFmkQrlsfWuULfRKZDe8kmHeBmiy3bPLJZbI14p2W0t+em/W6d9d16PIQ8pzcuXRszZXPahAFkBENuICVqQ5jM8wa6Qc1AJqU++IKsbsozlpUGQO/NtEw1UlDFbGqmaWxMHgl42u0235EIp3Fy23mgFM/wUdvxoyajCIYyV1HJnjVbY6pH4c1x11TDPrFbQcHeALznQHNpze//rlXqWFn0Oat8ltmQuSlmlo3Ms2FMEY8pXBU8RiZPtt9UlG+/0/5nuy+/YxlgYRGEz6J17UqeCPeU7+tORqKuii9rGL79bWu/BbVbSK61xsRPVACW0UdFiImUQJSvDhMcry8RKFoykvnPGc5ZmpKC0ZUe/hp/aMwIG+pKZI9aV/o= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2024 08:16:02.9977 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8cffd109-0d92-4297-5c84-08dd20ce8b70 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026367.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4103 X-Patchwork-Delegate: kuba@kernel.org From: Shahar Shitrit When creating a software steering completion queue (CQ), an arbitrary MSIX vector n is selected. This results in the CQ sharing the same Ethernet traffic channel n associated with the chosen vector. However, the value of n is often unpredictable, which can introduce complications for interrupt monitoring and verification tools. Moreover, SW steering uses polling rather than event-driven interrupts. Therefore, there is no need to select any MSIX vector other than the existing vector 0 for CQ creation. In light of these factors, and to enhance predictability, we modify the code to consistently select MSIX vector 0 for CQ creation. Fixes: 297cccebdc5a ("net/mlx5: DR, Expose an internal API to issue RDMA operations") Signed-off-by: Shahar Shitrit Reviewed-by: Yevgeny Kliteynik Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c index 6fa06ba2d346..f57c84e5128b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_send.c @@ -1067,7 +1067,6 @@ static struct mlx5dr_cq *dr_create_cq(struct mlx5_core_dev *mdev, int inlen, err, eqn; void *cqc, *in; __be64 *pas; - int vector; u32 i; cq = kzalloc(sizeof(*cq), GFP_KERNEL); @@ -1096,8 +1095,7 @@ static struct mlx5dr_cq *dr_create_cq(struct mlx5_core_dev *mdev, if (!in) goto err_cqwq; - vector = raw_smp_processor_id() % mlx5_comp_vectors_max(mdev); - err = mlx5_comp_eqn_get(mdev, vector, &eqn); + err = mlx5_comp_eqn_get(mdev, 0, &eqn); if (err) { kvfree(in); goto err_cqwq;