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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Dragos Tatulea , Cosmin Ratiu , Lior Nahmanson , Tariq Toukan Subject: [PATCH net 2/4] net/mlx5e: macsec: Maintain TX SA from encoding_sa Date: Fri, 20 Dec 2024 10:15:03 +0200 Message-ID: <20241220081505.1286093-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20241220081505.1286093-1-tariqt@nvidia.com> References: <20241220081505.1286093-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636B:EE_|PH0PR12MB7079:EE_ X-MS-Office365-Filtering-Correlation-Id: b464496b-d72e-461b-3c92-08dd20ce8ead X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: EWdtGyyG5AJMQgcYK9GOnpi9FcNZCNiy9mhnXawxFtz853k9utlqVzsR4jwZfhX7zTsqqtuP6E/QUXl/6isvT1H486UsTt3IR4e42f9rBqTX6YyFLOWU7uUhd0CsUXND+TDbebQwCMfzOmKCT++ZYakY5TAg9t/qKE/8ReiJ9w+ux+0zq88OqWh7KXiPReRSMKu7eJUuK/o80k5uKdc7ew00wR3jsvNFnLUZvGgYTch7RzBVCJxGFQFdmEiEE86+huKu3nt4iCe3sgvlOhcMMXP8U3EQKQstp4cuxtHZoO4nBb2OIx7RGVP6/lB0o6HyTrs0QeTPmKARVBqdbOh9d/mo/i3vOb9lUVbEMvpSa8ZQsJWWo2EvBmZ14c15JipHngFgpTum+y4CEZJqBwZqHiK0+XXkr4g8Dwp+yGJLokMlPJltdJ8ozDvTlB4AJpSBnhq3oTv0BYidQ3L1LE+Md3NfilMuI/dFC5SX0FHGcGHtpu241y+J4nZd3W1f7eJFAV6Q+H8nlsTL//EqJ+pMZPI+o1NA/XX7w24N7Tbw+zk7XQafD7D7JMGsgCG5gLrKwoPaWcCh15pX691ZqwQwmFe+L1ORJE0tUxQjXR2t3lJlU7bhXXBF5ZqbAtZlYikwyjN7ym/53jOwZBlbF/ihWYAdBNksJY+MijmE3pkvxYhVGuV9FNLkssmrMlecnAKL6q9hAlFm+tRMSIFHQtMePfsFo5QDbyXbHDfQj2o0CQzbgJPLBXc0k7aLYDS/WIcuqBVsYwTb74XEuRJqx75fey5sbIx7VzNRVd8UpEeAYwgmvNxBQviRLTAHqkDKBchgjoR5u4HK5iyuYHuaIXScrolTuNZPQ0YQZWiZvpdRYOIDH+FyZ+OpZONDOYp0HGrwgyzBdTXyX0gz/rpUiamULZuPvvj73hKU0Wkk5s+III1wpSPW9pUk01RU81Qdr+QbxUjcnuSlMec5GQ0NHThuLkh7vCfN+rGMHbQIN+oY8NUoTaykhLS0ykbOA5qCbEdDdtShnhPc8uIVm5EQ7SkTWEZteB5vkG1nqvlTRVX5Q02PsNWAFoH/uwK7sMrwzs8zHldX9YoDRsP9NbD1STBF7DfiuXKZrwLlgICM369gs5JQ0tbC6d7l7rBUZ7Rfci2J0sWFU9SQZpUNV6Q1UOllavvkNKOeZwQ2EloIRhcSovSJw5ufyM6Dow/lh1vNPFIEOXzKFEfSecoF+dKMuKaG8rT7m4R8mGMeZ6jTKMOkg+bs32/8DIztLxXMfKoAaF9nXdEwys2z/HwO0sTAnLxTXnmvTbnVqR2wGD+dPglvmJslKTeG4EGCPk6Se7lHv/JyHuqHWNmoiIoABSz+6COYXvkkZXZakwaD2wP/+esfDwvn6RFaBL4ouzE67m+kX/sW1K3AmAiQERJBnCB0bcVyZE6OEs8ahAdKBQTnSPSKNxFx88bMjj/UMT6gQjG/aamzGi70fzxbvuMM66T/VGitJCcaMT0khyM5nPPcEbGY+Po= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Dec 2024 08:16:08.4298 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b464496b-d72e-461b-3c92-08dd20ce8ead X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7079 X-Patchwork-Delegate: kuba@kernel.org From: Dragos Tatulea In MACsec, it is possible to create multiple active TX SAs on a SC, but only one such SA can be used at a time for transmission. This SA is selected through the encoding_sa link parameter. When there are 2 or more active TX SAs configured (encoding_sa=0): ip macsec add macsec0 tx sa 0 pn 1 on key 00 ip macsec add macsec0 tx sa 1 pn 1 on key 00 ... the traffic should be still sent via TX SA 0 as the encoding_sa was not changed. However, the driver ignores the encoding_sa and overrides it to SA 1 by installing the flow steering id of the newly created TX SA into the SCI -> flow steering id hash map. The future packet tx descriptors will point to the incorrect flow steering rule (SA 1). This patch fixes the issue by avoiding the creation of the flow steering rule for an active TX SA that is not the encoding_sa. The driver side tx_sa object and the FW side macsec object are still created. When the encoding_sa link parameter is changed to another active TX SA, only the new flow steering rule will be created in the mlx5e_macsec_upd_txsa() handler. Fixes: 8ff0ac5be144 ("net/mlx5: Add MACsec offload Tx command support") Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu Reviewed-by: Lior Nahmanson Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c index cc9bcc420032..6ab02f3fc291 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/macsec.c @@ -339,9 +339,13 @@ static int mlx5e_macsec_init_sa_fs(struct macsec_context *ctx, { struct mlx5e_priv *priv = macsec_netdev_priv(ctx->netdev); struct mlx5_macsec_fs *macsec_fs = priv->mdev->macsec_fs; + const struct macsec_tx_sc *tx_sc = &ctx->secy->tx_sc; struct mlx5_macsec_rule_attrs rule_attrs; union mlx5_macsec_rule *macsec_rule; + if (is_tx && tx_sc->encoding_sa != sa->assoc_num) + return 0; + rule_attrs.macsec_obj_id = sa->macsec_obj_id; rule_attrs.sci = sa->sci; rule_attrs.assoc_num = sa->assoc_num;