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client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by SJ5PEPF000001EB.mail.protection.outlook.com (10.167.242.199) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8314.11 via Frontend Transport; Mon, 30 Dec 2024 21:45:00 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 30 Dec 2024 15:44:59 -0600 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Mon, 30 Dec 2024 15:44:58 -0600 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v9 04/27] cxl/pci: add check for validating capabilities Date: Mon, 30 Dec 2024 21:44:22 +0000 Message-ID: <20241230214445.27602-5-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241230214445.27602-1-alejandro.lucero-palau@amd.com> References: <20241230214445.27602-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: alejandro.lucero-palau@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EB:EE_|IA1PR12MB7493:EE_ X-MS-Office365-Filtering-Correlation-Id: 4cce2c72-d4bd-4467-ee38-08dd291b3675 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2024 21:45:00.9470 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4cce2c72-d4bd-4467-ee38-08dd291b3675 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7493 From: Alejandro Lucero During CXL device initialization supported capabilities by the device are discovered. Type3 and Type2 devices have different mandatory capabilities and a Type2 expects a specific set including optional capabilities. Add a function for checking expected capabilities against those found during initialization and allow those mandatory/expected capabilities to be a subset of the capabilities found. Rely on this function for validating capabilities instead of when CXL regs are probed. Signed-off-by: Alejandro Lucero Reviewed-by: Zhi Wang Reviewed-by: Jonathan Cameron --- drivers/cxl/core/pci.c | 16 ++++++++++++++++ drivers/cxl/core/regs.c | 9 --------- drivers/cxl/pci.c | 24 ++++++++++++++++++++++++ include/cxl/cxl.h | 3 +++ 4 files changed, 43 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index ec57caf5b2d7..57318cdc368a 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -1055,3 +1056,18 @@ int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) return 0; } + +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, + unsigned long *current_caps) +{ + + if (current_caps) + bitmap_copy(current_caps, cxlds->capabilities, CXL_MAX_CAPS); + + dev_dbg(cxlds->dev, "Checking cxlds caps 0x%pb vs expected caps 0x%pb\n", + cxlds->capabilities, expected_caps); + + /* Checking a minimum of mandatory/expected capabilities */ + return bitmap_subset(expected_caps, cxlds->capabilities, CXL_MAX_CAPS); +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_check_caps, "CXL"); diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 144ae9eb6253..6432a784f08b 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -446,15 +446,6 @@ static int cxl_probe_regs(struct cxl_register_map *map, unsigned long *caps) case CXL_REGLOC_RBI_MEMDEV: dev_map = &map->device_map; cxl_probe_device_regs(host, base, dev_map, caps); - if (!dev_map->status.valid || !dev_map->mbox.valid || - !dev_map->memdev.valid) { - dev_err(host, "registers not found: %s%s%s\n", - !dev_map->status.valid ? "status " : "", - !dev_map->mbox.valid ? "mbox " : "", - !dev_map->memdev.valid ? "memdev " : ""); - return -ENXIO; - } - dev_dbg(host, "Probing device registers...\n"); break; default: diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index dbc1cd9bec09..9e790382496a 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -903,6 +903,8 @@ __ATTRIBUTE_GROUPS(cxl_rcd); static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); + DECLARE_BITMAP(expected, CXL_MAX_CAPS); + DECLARE_BITMAP(found, CXL_MAX_CAPS); struct cxl_memdev_state *mds; struct cxl_dev_state *cxlds; struct cxl_register_map map; @@ -964,6 +966,28 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + bitmap_clear(expected, 0, CXL_MAX_CAPS); + + /* + * These are the mandatory capabilities for a Type3 device. + * Only checking capabilities used by current Linux drivers. + */ + set_bit(CXL_DEV_CAP_HDM, expected); + set_bit(CXL_DEV_CAP_DEV_STATUS, expected); + set_bit(CXL_DEV_CAP_MAILBOX_PRIMARY, expected); + set_bit(CXL_DEV_CAP_MEMDEV, expected); + + /* + * Checking mandatory caps are there as, at least, a subset of those + * found. + */ + if (!cxl_pci_check_caps(cxlds, expected, found)) { + dev_err(&pdev->dev, + "Expected mandatory capabilities not found: (%pb - %pb)\n", + expected, found); + return -ENXIO; + } + rc = cxl_pci_type3_init_mailbox(cxlds); if (rc) return rc; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index c5e4b6233baa..464e5fb006ba 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -40,4 +40,7 @@ void cxl_set_dvsec(struct cxl_dev_state *cxlds, u16 dvsec); void cxl_set_serial(struct cxl_dev_state *cxlds, u64 serial); int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, enum cxl_resource); +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, + unsigned long *expected_caps, + unsigned long *current_caps); #endif