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Mon, 30 Dec 2024 15:45:01 -0600 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v9 06/27] cxl: add function for type2 cxl regs setup Date: Mon, 30 Dec 2024 21:44:24 +0000 Message-ID: <20241230214445.27602-7-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241230214445.27602-1-alejandro.lucero-palau@amd.com> References: <20241230214445.27602-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001EB:EE_|CY8PR12MB7730:EE_ X-MS-Office365-Filtering-Correlation-Id: ace072b2-e72b-4ae6-a156-08dd291b380d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700013; X-Microsoft-Antispam-Message-Info: 0pwd4SbmmWd6SRj5uCcFBcKXRVwThDmsKaF5VZ0tWSodDjVxpeSgCKMrQ86VpqAqkH+7MSdvSDEKuFjcbruTBvFlKL1J3nD9LBBDQiaFmOz7cvqD2mcwOzhHc+mX1FMNEEFAlYS57iH7SEpyv56/3Y/zpJz6aulpVS7/W2P/27ibZxXX403Nmqg+KsOaztBNx9uaRnHzpQDI5Or5tmEQlhbKuA2W0n+ImcYsxu9LQ3Zp+K06G0VhLFPhYrl8luMrPgbdl9uhAFt7KivtlTfLgkedfCn37WjyCR/yrxtJBrJuFdOy1QmXKvgKKcA6L42lfE++5/nvTYGiXg/dsEPpwkQliPeC8S7RJ15yFydsGp3fhO6urZGCdhfsMhcLvIOEbdHhoQWFSZFlIQr+6GogiR81dbC/7PzX2ubeQJ2gi70EID2htoQB7O2vUhsxRlwV3DGwsJNG5olpljidVXrOPB0U/ZudN2e/+Rhph4ikvzKl4UDyeE5Q3eW1hq0oMRBtq2it6zGop9Tt/OsNE1IYv+b30+pgv7wPMdEfY1sKIE02kCTDSOjAl3jQiFHJSp/9Zxb60n9d4h63svDcIIp16rMWvi0Dr8DWkdmulSzPsbX1dh4punCVuXu2Nj5ghKOrhFchd8rn+mkU0ClJtthF1wePtmuGkoe4/meDzFfh8AokWqOwg8/Gj6VDseeXPbqI2PT5zeUX3nqOG06qR/xrGjL1b06CKwV8bd7q5qWAYn+43GzhS9NCKLjK27vbLPAns0eKfX/vVLJKtqmooEd1CnCS0QbZlzAVGsuqbd6LzZX8XkpgoGR0rbxF12SlgQFdCyUt2c9w1Ykvm4w5iULbKTtD0cJ3KD63KziI1MUvDaqiXwtk1JoLfg+H4Mx9icg6olFkqbTwuwkuataJ+qI1mciwby5ris4pbiulEsiDW99SDwDexRxZ1+sR/xjCANh1GziwZml36ETHncj+ezrp/C+BFkuLpAflkQPryEE9OBAXydhT6luC+PmM+7M9ice1OFC8Q2+vX2iSy6eQXoQNkY01zsbMbLPypTUXJCzsjBhOzrtlJR/xaK3y4+/mvqLL0x+gQRWqfgSbcxOVvNC03PU/xQVDtjuHxLG54uRPOG03BmT5xnqoSzaXG+dXsN5oy9/5fX5GLNpZkl66lXdF6tpAlXsPYG0XvkpzZfBpzacRrWc4L1Rb7UvHGcoBr7JX9Ga5sAB7bH1gJ7xUmhypLDDqJhJZVE8DpoERWV9WP9FzjKexjHVjHJyje3kjZJ76W88rReYXXO3MdlpZYhQs56SsPrGSv8fSdPuQTW3afnl8qOUDy2LQEioNgt+GvKhJoZUBF/R4h7zrb91YFoMt2J0uQ6Og2aK3WZdl23QB393Rg9MgQAIClpo/NMlLk30l2afakk1NqfvJfvEDhouk7uY+FqR2T+OTk7FkfgdX7Ya/xmjHkFTgy/g5VNa9H/782nBPreRacKmXD6exICcaDGpKajDkpVdNbPVUmraVKkg= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Dec 2024 21:45:03.6189 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ace072b2-e72b-4ae6-a156-08dd291b380d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7730 From: Alejandro Lucero Create a new function for a type2 device initialising cxl_dev_state struct regarding cxl regs setup and mapping. Signed-off-by: Alejandro Lucero Reviewed-by: Dave Jiang Reviewed-by: Fan Ni Reviewed-by: Jonathan Cameron --- drivers/cxl/core/pci.c | 51 ++++++++++++++++++++++++++++++++++++++++++ include/cxl/cxl.h | 2 ++ 2 files changed, 53 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 5821d582c520..493ab33fe771 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1107,6 +1107,57 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, } EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, + struct cxl_dev_state *cxlds) +{ + struct cxl_register_map map; + int rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, + cxlds->capabilities); + /* + * This call can return -ENODEV if regs not found. This is not an error + * for Type2 since these regs are not mandatory. If they do exist then + * mapping them should not fail. If they should exist, it is with driver + * calling cxl_pci_check_caps where the problem should be found. + */ + if (rc == -ENODEV) + return 0; + + if (rc) + return rc; + + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); +} + +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) +{ + int rc; + + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); + if (rc) + return rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, + &cxlds->reg_map, cxlds->capabilities); + if (rc) { + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); + return rc; + } + + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) + return rc; + + rc = cxl_map_component_regs(&cxlds->reg_map, + &cxlds->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS)); + if (rc) + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, "CXL"); + int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) { int speed, bw; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 464e5fb006ba..c1bb0359476c 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -43,4 +43,6 @@ int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, unsigned long *current_caps); +struct pci_dev; +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); #endif