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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Erez Shitrit , Tariq Toukan Subject: [PATCH net-next 11/15] net/mlx5: HWS, fix definer's HWS_SET32 macro for negative offset Date: Thu, 2 Jan 2025 20:14:10 +0200 Message-ID: <20250102181415.1477316-12-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0E1:EE_|CH3PR12MB7499:EE_ X-MS-Office365-Filtering-Correlation-Id: 280d17dc-8bae-448e-57dc-08dd2b598186 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: wZ/E9k9lWCQl8s379survqPQfS0ZBKWEi+HWHudQ6Hb+KztNUqyP1YafxjBDztQltUPUq45sRLFgJUD+c/2/A3x1jwocytCRO93cbokKR4xty+KVENGIJMdBN07LT5y/ARSaAsO4ke9CBnY0Al3hIAvJbGJLm7BSR+EdPIHXMI89JJKvHPFyl/wJdul3DxaJkfYJZyJzMnyp85D9868c2RysjC/repTrOIZ6LK4nqYLobDy+X3iRurn4rI5FtaU5YEsYCRtJT9Be8tj0YZWy6ybkNh21ilBdoZXiW8gA+J3RCrgzjnE0AMOpfvdYvpKqJ4ofyIUs3Pu92BNqp4TOI4b6pXhWjEcGO40NyHuGYTBLrjSdnfU00gvKy/GPuoj9zyVAcU50NO+nxxJKBmreR9gszEcFDtS+NE28VMBAmRBF7P4wbs1y0eYaQZWu5QlAkCtBqpD294UljxWV4YSjf2dCUPUaeRe2hJdfwqkTH33G1A6cyLEXoErItStE6ktxWn6G/RP1J9gJiY0lM2IqKhZwCof6bFl3MExZJAnEPyHOz6XFYnPYxR/yGcDHZcG91thJVYBGkQ1b714pt3CUcG7giZJNFYIcJrwA1hcbqc/4pEqL5p53rflYUR9uJc2beEsxALrvmz+r+AArqyg4rZwl6wh2/s2grqAbQbwnYrEKokKO24BsB1DxJpwdomgOiCeH+VNvD6FwliT9q7WDO/yIu660H40FBtWLyXpDAJN3c70mupGlzz7M3nS6eBPPKo+GFE41+jqgsbiOb9zz2FNrB+BITX5FbQ0nYf6rR0p/fPeIGfST0td+IsBzt15dWrJu18NbXMd7nnv5ww/fSfwXb6RnebIj2p6OEifYC0s3dHcraAULwIAXKLen8jUBQIRRyFB70GNZ7+G0bT4ip/VKcODT6XE64QnfypUlNxg+RJyoGqXYD1om1HbMzh1TsGTa4bXmq2zLtByEfuBzmYLcmS6oHDIcviN6t4Yei6g/xVBOucMvDvmdWP9lXGrSWBqzjiRX3DtaLK322K2DgFCGztsyZWzOG3iYmSlV2SGvi62DgqDZvw9GJxacvTaBKlEks5aTXPiBFwXMr8ECh6X+8n2eZIDvtxth8H9GL2mqJlUsBA45Qrxf1nfDyc/jOLxRFOopeKccCDr82xOTSruSNcjk7Nvv8b71+yxXs+8oI10H9WT6Tg2AujMNqSBNWlLTgdgg3neFYPxvjqsFqIXNDJf5svhndsq3LwUFREZkjB7YP5m5OiTXyLdnSGy+jKX5uF3+nkx6XPV9z4DDCASm29v/aAXlTUT2rPArM0UYsNos4Z7TB3yzgiKi+8j+3/5HSHTo+PeAkecOpeQ5y66jU5qxOiZL7G1cA2p/Wp44Fx2SALoRunGm+BqpBagXHFnN2lYLrFDH+E0YT6JHZZpGHB7OzJZgDHNT0WmSSkWQH8uhtrXTbqlpWi7kNloUhNOaAWjibbgcv/3w/llV1o5IQkI3JWZTczOfDngzhmU= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:15:57.9752 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 280d17dc-8bae-448e-57dc-08dd2b598186 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E1.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7499 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik When bit offset for HWS_SET32 macro is negative, UBSAN complains about the shift-out-of-bounds: UBSAN: shift-out-of-bounds in drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c:177:2 shift exponent -8 is negative Fixes: 74a778b4a63f ("net/mlx5: HWS, added definers handling") Signed-off-by: Yevgeny Kliteynik Reviewed-by: Erez Shitrit Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c index 8fe96eb76baf..10ece7df1cfa 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c @@ -70,7 +70,7 @@ u32 second_dw_mask = (mask) & ((1 << _bit_off) - 1); \ _HWS_SET32(p, (v) >> _bit_off, byte_off, 0, (mask) >> _bit_off); \ _HWS_SET32(p, (v) & second_dw_mask, (byte_off) + DW_SIZE, \ - (bit_off) % BITS_IN_DW, second_dw_mask); \ + (bit_off + BITS_IN_DW) % BITS_IN_DW, second_dw_mask); \ } else { \ _HWS_SET32(p, v, byte_off, (bit_off), (mask)); \ } \