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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Vlad Dogaru , Itamar Gozlan , Tariq Toukan Subject: [PATCH net-next 13/15] net/mlx5: HWS, use the right size when writing arg data Date: Thu, 2 Jan 2025 20:14:12 +0200 Message-ID: <20250102181415.1477316-14-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250102181415.1477316-1-tariqt@nvidia.com> References: <20250102181415.1477316-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000F0DF:EE_|BY5PR12MB4066:EE_ X-MS-Office365-Filtering-Correlation-Id: 48f7d090-9dbd-49c5-9bd3-08dd2b59882f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: zNauqgzTRKwE7eGHGDPw58NHXrTchP/omwpIeXV9YE14e23jopzosQIqEMN1KdRuZfGbQBCRhlckl3MJU0Y5S3sT5DMwLA5jG8VPLmwcscNJ3YIa2qgVpig+wkncPxptEax8KFlown9aNqlPkPUWvzkUaDx4sN4eECdMnm3p3xHtLBoaq1bIxIjpZnDYH43cvd4vn45/xKueuPr3bEfAtk5dIUkwsfLvj0usFkorPku+3TnU0+JIXEjWgs9DdzKIeVKKfPx4vDGA7Xu6edDfbKlW99zpMsDtGNNhmCJvI6T35Y67JDMBKdAm17E8sAjzIyLh+SLwWliWTPIW7TEJLabxVQaZHZ3RrYhSF9vLJhxu8Pgre3Bze0YSJncN8y8HwE/LDWz7vdPue85apsG9Lc+DKzrACJvtiMGgPcCnn9mITUEy5cifxzRaAhMo6OmFkhQo3gc2QsUn+0/NEUZeA+dMPSCzvndQJdNKkFNrHKXCrHjNK1VQnyZBdAKbBeYhapKAajKoA4bMV7+HwPsNv7AL95BZBqS1W+Vbs0SPRe0oSG9KmdqkzHG+/XTXRAobxO71DZIIR6+c7MRSIG7vOAWNmE/0ellgNG1Hn0BEouCWcaW05i5L1wfUd/72FHUOPfeLTnsTmVe/E9r9BpSfssd9+6Gz8K1kQWIzORORucn4ggosyNq9NvnaHy/sFYcQhMUEp9pwsSHqjftXo50fS0TPBSekoxGcFV5obv7gVa4a117fxeoNIVVKctXJhAKqGEU3I8UVqs6S+pj1q+w475+5Pud+F3yFSsxxRngAYlvhbY1fzDqVCgbK/usEwddg4o8xSfLwXXg3Y0fOzwAui6p8rX3xYsY3rpPrDZ2/hh0Z5LPzjJl4w25mn/ZFsqDp2ib++vX9GB6el/FxPhuZmwrc2HkDco2zIP1WINaoQx9OFlBf60RvmYhuFKz3sPUZtyOu8xDD2OvdeS9Il5AHGKvjugOeKr2evnoNxTg1K4gbqeN8FHwpvirWzDV4vdIyT6mBFlpOQb5mMF2EbzPmWA/2GVfpDRUtGhw3Z3QcF1FC9uYR7tExQaECe+iZzoNzWc1uDLBgXufpxjIdwJScS5/iv59FXL85+WSLKynRUagkhLDBW+F5EOPPREb9wZKNTzc5mj+RcL+1AhjSDABGiMD4inhXItg3Aa/ixpZm+2bQ/ERWqT0iSOJSjl2jMGEDtyav9Yr8cj/RBviVaZsbyu+piTOfKoYc0sb0D1CSjLFi1evVfoM0gf5H0CFBdNPYwImbZ5GwSdZEOCHvhUp7yrLM8Xcwnjjmd3HC2qtukFpGMZG1qjtrq23xnh/uDtEfJL3gbwulBmeGt0s1psGSmoiHiiXH8G+VAk2Spu8w4K0vEdoZ862XvVVztYlo66HyPDtO67hwkbwgO5yTAwhY5pTsp7+zu216/LHnVK5zgAD20SpyRq20Cj9QFmsu/iquP7ywj+NnXVRiQEaylLbS2A== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jan 2025 18:16:09.1508 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 48f7d090-9dbd-49c5-9bd3-08dd2b59882f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4066 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik When writing arg data, wrong size was used - fixing this. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Itamar Gozlan Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c index 06db5e4726ae..d9dc4f2d0dc6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c @@ -344,7 +344,7 @@ void mlx5hws_arg_write(struct mlx5hws_send_engine *queue, mlx5hws_send_engine_post_req_wqe(&ctrl, (void *)&wqe_ctrl, &wqe_len); memset(wqe_ctrl, 0, wqe_len); mlx5hws_send_engine_post_req_wqe(&ctrl, (void *)&wqe_arg, &wqe_len); - memcpy(wqe_arg, arg_data, wqe_len); + memcpy(wqe_arg, arg_data, MLX5HWS_ARG_DATA_SIZE); send_attr.id = arg_idx++; mlx5hws_send_engine_post_end(&ctrl, &send_attr);