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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Tariq Toukan Subject: [PATCH net-next 01/13] net/mlx5: fs, add HWS root namespace functions Date: Tue, 7 Jan 2025 08:06:56 +0200 Message-ID: <20250107060708.1610882-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250107060708.1610882-1-tariqt@nvidia.com> References: <20250107060708.1610882-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009F:EE_|PH7PR12MB6907:EE_ X-MS-Office365-Filtering-Correlation-Id: 59cedafd-cf6a-4bfb-8584-08dd2ee1b80f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: 0ZfmuyPhbf3Y8sGgn8MncB/a64kTQj42VFuDU7A1vdzrclEBqaeM/XVPgxzrV4707F/hG+EOiB1j0ac5XcZ4ajFJDkGEX9hDTUns86FrnbAvEyBPS0QTfUzFurgagQNSjvQEFfnOo/PPXqs48P1J7E9CGXe/gjQC8wJhOgteY00BwQJjDhMME6/t6zMFtnekMhIARkAMPs3Zd6lcNdg0nXTu6oUATpBCXgD9BAnoQYwRYRBhuFj0rkHyWQMeavrAIkO6y0TLdA50oTR6lDtIyjgljSCF/DMrLZl5/Oxp5tjugWAQKNvkhk0B+EMcazp8pPyTBENht6HDjfkheDHTetGRwdIIBEZrjdK2l0uykAxkSCyigJb5GvfCxIVrSEDGHiDPovnqSP8388+Rr3sdMQw8IcWMCpJNWCtWwLB8RG5iH3GZbyqA/OyyS/9p7HcnPbLF27ZaZ3dQjgkpOHC/rs4G2Vb6tm2H9VN8ZdAL+fT6dXh1r7SjWr6UiTvZc8N+lWQZINaBugbEs86ZV/3GUBthPszyd1AcF3084r2/5glcmvM3Vo00PjNAELY8dz5XfpBChNJMqXGobEakhQRzV00Xxwn8uecTRLvdGqq9NJb6wbXeFqKVuPf1sgnDB2U/h4/4g5GQI6ma6aXYVTdaL2y7oiw+z8ACz3dyOz4cP7O61kH1XW3S/mea9F3AMz4f0PGUyYJKFs3R1fefxvtfOc88yN/t8oHzr46MimagqEKdYHqiRGfc1ulHXbyeBvi1brCWTapA2Ttgd9GbZP/K0rlbyMoER5IBf5BKwOtyA99ZOicXX7DCdjtwJ3QOWAv48hTFmx6f3BkWYAExPsW1BP6KWNHwwFa/M5ZIHsbwL4Bf67BrKuZpZS0PZ5gyTJFqmzORLFaIAPaA5XyeNU/D95YU/qDdLMuSxThzUT4G3RMxBLcVpn9iPJNoLbjHcZHxR5uOejh+L0jmHsM+4eziMxJ/pcePeqlR2W8Cnd1gY8q0c5ez96jViV5S4RPEHeXHEB+gAAkzE3JmiNgG3L1I/tiMejBaO6bCkr7oCqUDtqgCjHqEqyV30qX8JbUZqXS002l067dXxCYXIRGovsWqvTei6OKKu9ZGSXTOc1DNaWJBm8R+IierNaRuan/MfOYwuH7sL20z2orpBcefLpOAPDUs6CmWeuxxibpY8bzi076auKs9oMXWILxu81ayW+TWRjg/buMflaRFn1r6AtWHXMe2zp5h5pgUEBeskSCg7XCb0Udh07pYOO6+gWYDr9Q75yhGGW+YiLEZjJnpVJsS5z1cesP1mZclt5K8ULCrUXBZGKwGT+d1Huuxuk4Z5vZpF73i3GBPE6TgMM9u5jfJZPb/g+frAzS0zlWTA1+z3EyYkww4GWbddypKB6Ah/PirXczFjZO2poFQi8C5o6hCblwpKM7VOH4jKNJgbHqyZsMZlr4ussh60Gtp8GsohzQTob2L9mloU9dMjLjxjHe/5LnNGxBk0cSOfbC0MvhAxiI= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jan 2025 06:08:34.5460 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 59cedafd-cf6a-4bfb-8584-08dd2ee1b80f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6907 X-Patchwork-Delegate: kuba@kernel.org From: Moshe Shemesh Add flow steering commands structure for HW steering. Implement create, destroy and set peer HW steering root namespace functions. Signed-off-by: Moshe Shemesh Reviewed-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/Makefile | 4 +- .../net/ethernet/mellanox/mlx5/core/fs_core.h | 9 ++- .../mellanox/mlx5/core/steering/hws/fs_hws.c | 56 +++++++++++++++++++ .../mellanox/mlx5/core/steering/hws/fs_hws.h | 25 +++++++++ 4 files changed, 90 insertions(+), 4 deletions(-) create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.c create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.h diff --git a/drivers/net/ethernet/mellanox/mlx5/core/Makefile b/drivers/net/ethernet/mellanox/mlx5/core/Makefile index 10a763e668ed..0008b22417c8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/Makefile +++ b/drivers/net/ethernet/mellanox/mlx5/core/Makefile @@ -151,8 +151,8 @@ mlx5_core-$(CONFIG_MLX5_HW_STEERING) += steering/hws/cmd.o \ steering/hws/bwc.o \ steering/hws/debug.o \ steering/hws/vport.o \ - steering/hws/bwc_complex.o - + steering/hws/bwc_complex.o \ + steering/hws/fs_hws.o # # SF device diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h index bad2df0715ec..545fdfce7b52 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.h @@ -38,6 +38,7 @@ #include #include #include +#include #define FDB_TC_MAX_CHAIN 3 #define FDB_FT_CHAIN (FDB_TC_MAX_CHAIN + 1) @@ -126,7 +127,8 @@ enum fs_fte_status { enum mlx5_flow_steering_mode { MLX5_FLOW_STEERING_MODE_DMFS, - MLX5_FLOW_STEERING_MODE_SMFS + MLX5_FLOW_STEERING_MODE_SMFS, + MLX5_FLOW_STEERING_MODE_HMFS }; enum mlx5_flow_steering_capabilty { @@ -293,7 +295,10 @@ struct mlx5_flow_group { struct mlx5_flow_root_namespace { struct mlx5_flow_namespace ns; enum mlx5_flow_steering_mode mode; - struct mlx5_fs_dr_domain fs_dr_domain; + union { + struct mlx5_fs_dr_domain fs_dr_domain; + struct mlx5_fs_hws_context fs_hws_context; + }; enum fs_flow_table_type table_type; struct mlx5_core_dev *dev; struct mlx5_flow_table *root_ft; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.c new file mode 100644 index 000000000000..7a3c84b18d1e --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB +/* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ + +#include +#include +#include +#include "mlx5hws.h" + +#define MLX5HWS_CTX_MAX_NUM_OF_QUEUES 16 +#define MLX5HWS_CTX_QUEUE_SIZE 256 + +static int mlx5_cmd_hws_create_ns(struct mlx5_flow_root_namespace *ns) +{ + struct mlx5hws_context_attr hws_ctx_attr = {}; + + hws_ctx_attr.queues = min_t(int, num_online_cpus(), + MLX5HWS_CTX_MAX_NUM_OF_QUEUES); + hws_ctx_attr.queue_size = MLX5HWS_CTX_QUEUE_SIZE; + + ns->fs_hws_context.hws_ctx = + mlx5hws_context_open(ns->dev, &hws_ctx_attr); + if (!ns->fs_hws_context.hws_ctx) { + mlx5_core_err(ns->dev, "Failed to create hws flow namespace\n"); + return -EOPNOTSUPP; + } + return 0; +} + +static int mlx5_cmd_hws_destroy_ns(struct mlx5_flow_root_namespace *ns) +{ + return mlx5hws_context_close(ns->fs_hws_context.hws_ctx); +} + +static int mlx5_cmd_hws_set_peer(struct mlx5_flow_root_namespace *ns, + struct mlx5_flow_root_namespace *peer_ns, + u16 peer_vhca_id) +{ + struct mlx5hws_context *peer_ctx = NULL; + + if (peer_ns) + peer_ctx = peer_ns->fs_hws_context.hws_ctx; + mlx5hws_context_set_peer(ns->fs_hws_context.hws_ctx, peer_ctx, + peer_vhca_id); + return 0; +} + +static const struct mlx5_flow_cmds mlx5_flow_cmds_hws = { + .create_ns = mlx5_cmd_hws_create_ns, + .destroy_ns = mlx5_cmd_hws_destroy_ns, + .set_peer = mlx5_cmd_hws_set_peer, +}; + +const struct mlx5_flow_cmds *mlx5_fs_cmd_get_hws_cmds(void) +{ + return &mlx5_flow_cmds_hws; +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.h new file mode 100644 index 000000000000..a2e2935d7367 --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/fs_hws.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ +/* Copyright (c) 2024 NVIDIA Corporation & Affiliates */ + +#ifndef _MLX5_FS_HWS_ +#define _MLX5_FS_HWS_ + +#include "mlx5hws.h" + +struct mlx5_fs_hws_context { + struct mlx5hws_context *hws_ctx; +}; + +#ifdef CONFIG_MLX5_HW_STEERING + +const struct mlx5_flow_cmds *mlx5_fs_cmd_get_hws_cmds(void); + +#else + +static inline const struct mlx5_flow_cmds *mlx5_fs_cmd_get_hws_cmds(void) +{ + return NULL; +} + +#endif /* CONFIG_MLX5_HWS_STEERING */ +#endif