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Sun, 12 Jan 2025 22:40:15 -0800 (PST) Received: from lvnvda3289.lvn.broadcom.net ([192.19.161.250]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21a9f254264sm46488165ad.233.2025.01.12.22.40.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Jan 2025 22:40:15 -0800 (PST) From: Michael Chan To: davem@davemloft.net Cc: netdev@vger.kernel.org, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, andrew+netdev@lunn.ch, pavan.chebbi@broadcom.com, andrew.gospodarek@broadcom.com, somnath.kotur@broadcom.com, Hongguang Gao , Ajit Khaparde Subject: [PATCH net-next 07/10] bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings Date: Sun, 12 Jan 2025 22:39:24 -0800 Message-ID: <20250113063927.4017173-8-michael.chan@broadcom.com> X-Mailer: git-send-email 2.43.4 In-Reply-To: <20250113063927.4017173-1-michael.chan@broadcom.com> References: <20250113063927.4017173-1-michael.chan@broadcom.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Newer firmware can use the NQ ring ID associated with each RX/RX AGG ring to enable PCIe Steering Tags on P5_PLUS chips. When allocating RX/RX AGG rings, pass along NQ ring ID for the firmware to use. This information helps optimize DMA writes by directing them to the cache closer to the CPU consuming the data, potentially improving the processing speed. This change is backward-compatible with older firmware, which will simply disregard the information. Reviewed-by: Hongguang Gao Reviewed-by: Ajit Khaparde Signed-off-by: Andy Gospodarek Signed-off-by: Michael Chan Reviewed-by: Michal Swiatkowski --- drivers/net/ethernet/broadcom/bnxt/bnxt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt.c b/drivers/net/ethernet/broadcom/bnxt/bnxt.c index c862250d3b77..30a57bbc407c 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt.c +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt.c @@ -6922,7 +6922,8 @@ static void bnxt_set_rx_ring_params_p5(struct bnxt *bp, u32 ring_type, struct bnxt_ring_struct *ring) { struct bnxt_ring_grp_info *grp_info = &bp->grp_info[ring->grp_idx]; - u32 enables = RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID; + u32 enables = RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID | + RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID; if (ring_type == HWRM_RING_ALLOC_AGG) { req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG; @@ -6936,6 +6937,7 @@ static void bnxt_set_rx_ring_params_p5(struct bnxt *bp, u32 ring_type, cpu_to_le16(RING_ALLOC_REQ_FLAGS_RX_SOP_PAD); } req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx); + req->nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id); req->enables |= cpu_to_le32(enables); }