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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Tariq Toukan Subject: [PATCH net 8/8] net/mlx5e: Always start IPsec sequence number from 1 Date: Mon, 13 Jan 2025 17:40:54 +0200 Message-ID: <20250113154055.1927008-9-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250113154055.1927008-1-tariqt@nvidia.com> References: <20250113154055.1927008-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A3:EE_|SJ0PR12MB8115:EE_ X-MS-Office365-Filtering-Correlation-Id: b92c632b-f0f7-442b-9d70-08dd33e8e1ca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: T3Wb8xQOgRVQE5eLbQLkI1EFN0ZwVnpWvivEk0fW9LBOArMnYzbZZDtUnhS0pNmZn/e2bcO+EPWpHp33y/vbapAbzVR0uyYVSRkxsUNKe6UlZER9gMX/NPsirI6VFPOl82e41YspWE9BaRg91sMxraKyr9OgTHTO0HZlk26JB2kfpkZI35NPtDCE7iB4PSaHaGsOZ+GRnD5ei5YPj9yG84dj9MRc8C9OLcsnzpp0/GDfahxzYZ2dZMjtecubromHGlC0dThgkxGASWxmEmMl7Q1WBDhROuERr8QJgrJGF7Aa8IggQwlV7GHDzC38jbYWGWhjvTje19iWbOMsSHmi1rvwP4l5L177x/M8kY+XssOYR/H2rmTI8+NELW/vqjTilLIp4Q1zxB6eK1P70MidzKAvvfQlkk6sBTE591fVd6fGrSphqkPyZv0Gdf0v0wVv+ypRC/VZwjxyOQOtzTJBEYAfqgO6LOUU1qb9YiLlzPF5SStwgSnPrIBgabQOy4WaQoAEj/3+tD4qB2kxhTY2yo6SrdTIhynOwGXIAoI/edIRyjDNHWmVtCWWDBm4rSxypvPgeqZS48K+WH0bLEDPKFR5lISTLF6Z7YCdPYFf0NSz44B46r3M3YSudHsRXV3zTR0cnw8WQsa5mZumhp2gGM044/bPPl7PS87i7zqm11YjRN8z8r97Lp3wViuo2tH2oSJmQepD2X0+3rmwpsKSc+eXbEmSPfylrAmqUuxweF52pAugZsXj8Ug3xJM9msbSpq8o8euu4hFysRa78D6++LCcBlwIecx1wJn1RhMS59zPyXsn6lbsCZZ9XHz3W87RlkA6KtpHFgO8GZ4Ng2zUWQf/XwTssZdCC3Pnlp4Qez/OTYqZMNH+ybn+nda7+6LP1vfTlp/Rs4Lr+cUKjt7SxRfcdhvB4DuwkKLKw9co5ScTC1l9hnM6Y7zdC9HHHl2hIfplc2Y2QrcLpp1pkws17Cx3h8XTugESzX3fr5kcAQBFomRgN0LzkAvxtKo1b2GwsIFJG1zOEa6d0n0V6eNDgi0WcEMw0sn4KZtq6rOyRctDO2ybm/NDePhj1YYIWEuwEphIS4Ct4w4skLxfFXus7fizNf7Uvq2XVMU2QNvNgQSL92N3KankEuB32RsdjwO86VDc2JvbS/5Px9ACJgvgVQMNbGEOjKQjCH1b8A1jiCSNvVaG6xxO+UMQTmqm0ycN8twEDUEHDVgJeuavf0lOxBDiSg/qLl+0FxXWApHcqd16etFgDZAzFjRun8hsBFPBGihC2U5LPpL8fIoVl6Kv7DzoHnO7zvYUgrDAiV+/JpWrtk6WdDrswaAu6s4ZrnyzkvpZmmVMxoJfbtJqrvZUSpbRpfoZ2Hfco1qYeJg4TO2DAHNTv1s7CnWkF8PWijAEa80gN6yjTTyOjKBxmAcpLC+q9M8QDzyfFULWk2CUPrsxVMZEEgxo+KUpv1ZX7gScFW6TOgme8zheSZeQp4TVH+iWLZNsfbK6Lk20m0212O4= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jan 2025 15:42:26.8809 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b92c632b-f0f7-442b-9d70-08dd33e8e1ca X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8115 X-Patchwork-Delegate: kuba@kernel.org From: Leon Romanovsky According to RFC4303, section "3.3.3. Sequence Number Generation", the first packet sent using a given SA will contain a sequence number of 1. This is applicable to both ESN and non-ESN mode, which was not covered in commit mentioned in Fixes line. Fixes: 3d42c8cc67a8 ("net/mlx5e: Ensure that IPsec sequence packet number starts from 1") Signed-off-by: Leon Romanovsky Signed-off-by: Tariq Toukan Reviewed-by: Jacob Keller --- .../net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c | 6 ++++++ .../mellanox/mlx5/core/en_accel/ipsec_offload.c | 11 ++++++++--- 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c index 21857474ad83..1baf8933a07c 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec.c @@ -724,6 +724,12 @@ static int mlx5e_xfrm_add_state(struct xfrm_state *x, /* check esn */ if (x->props.flags & XFRM_STATE_ESN) mlx5e_ipsec_update_esn_state(sa_entry); + else + /* According to RFC4303, section "3.3.3. Sequence Number Generation", + * the first packet sent using a given SA will contain a sequence + * number of 1. + */ + sa_entry->esn_state.esn = 1; mlx5e_ipsec_build_accel_xfrm_attrs(sa_entry, &sa_entry->attrs); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c index 53cfa39188cb..820debf3fbbf 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c @@ -91,8 +91,9 @@ u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev) EXPORT_SYMBOL_GPL(mlx5_ipsec_device_caps); static void mlx5e_ipsec_packet_setup(void *obj, u32 pdn, - struct mlx5_accel_esp_xfrm_attrs *attrs) + struct mlx5e_ipsec_sa_entry *sa_entry) { + struct mlx5_accel_esp_xfrm_attrs *attrs = &sa_entry->attrs; void *aso_ctx; aso_ctx = MLX5_ADDR_OF(ipsec_obj, obj, ipsec_aso); @@ -120,8 +121,12 @@ static void mlx5e_ipsec_packet_setup(void *obj, u32 pdn, * active. */ MLX5_SET(ipsec_obj, obj, aso_return_reg, MLX5_IPSEC_ASO_REG_C_4_5); - if (attrs->dir == XFRM_DEV_OFFLOAD_OUT) + if (attrs->dir == XFRM_DEV_OFFLOAD_OUT) { MLX5_SET(ipsec_aso, aso_ctx, mode, MLX5_IPSEC_ASO_INC_SN); + if (!attrs->replay_esn.trigger) + MLX5_SET(ipsec_aso, aso_ctx, mode_parameter, + sa_entry->esn_state.esn); + } if (attrs->lft.hard_packet_limit != XFRM_INF) { MLX5_SET(ipsec_aso, aso_ctx, remove_flow_pkt_cnt, @@ -175,7 +180,7 @@ static int mlx5_create_ipsec_obj(struct mlx5e_ipsec_sa_entry *sa_entry) res = &mdev->mlx5e_res.hw_objs; if (attrs->type == XFRM_DEV_OFFLOAD_PACKET) - mlx5e_ipsec_packet_setup(obj, res->pdn, attrs); + mlx5e_ipsec_packet_setup(obj, res->pdn, sa_entry); err = mlx5_cmd_exec(mdev, in, sizeof(in), out, sizeof(out)); if (!err)