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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Moshe Shemesh , Yevgeny Kliteynik , Tariq Toukan Subject: [PATCH net-next 1/4] net/mlx5: HWS, rework the check if matcher size can be increased Date: Tue, 14 Jan 2025 15:06:43 +0200 Message-ID: <20250114130646.1937192-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250114130646.1937192-1-tariqt@nvidia.com> References: <20250114130646.1937192-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A6734:EE_|DM4PR12MB8499:EE_ X-MS-Office365-Filtering-Correlation-Id: 4fbc9dd5-eb1d-4a05-70da-08dd349cdd02 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; X-Microsoft-Antispam-Message-Info: kKETkINQHyieXbn81+Fd4IjCyS4425bYclpAmW8CyE6EX3KE5mtKbHUjiWwIs5U3LM0XTaxu4S2kRBJ2YuPd0fdczwiHFBaagLt1/sxLz2c278fnmIalPD5J7VydcbsexnfgbiodMs+0ezexH77X3bIXNjZZJTYxqq15yI6HVrnIZDi0z5SXkWei1HfsIpSYQo03N9U3IhdLZu7xC++kkHrtypj3AoggD5iZaeneGTS5tKCTMpgNDTqesoLo3F8/Xpsi7vXyn/g78L0VSQNQ1BEUooaX0UUpRXP0u8U7A2y6HyyAjeVc+NsLucK3lIxs8rUqmHe5RMA1skisexr0WhXHleDSAtBEv1Imh2XWUpgFZQy5g2u+8X0DI8BksvXB9R+Mckqm+nL6YrLCwqovS5OntlXGkS+k+ldyCSvN8MYxCN7J47zEwW7csFCRDwcc4pHlBEKiUDtJK13sohAbOelxo8FTq8XRibY9uU6vUPSxssoBaA4oh5mhrAEYINekfyB8CpiERedPTmhoZ2dY4R+Zg8uZzlvpTvISPE0ZkaD0B+/SliO9zBF9X9ELdeWljz3AVWEEYw+4O8nhGwQqIqiCHSb94vkWMc3qtfZbxmBLTT/Dff8uoT6a7Uh7K8yppEiSZ03GK9wHdS2KLoMjg8+KsIJmHWON954nmRB7MeHtzvpX4a6dah/xvmCKKhC6TPmfVmXqQ1/KYvfTGFA25AHi4MHTDJ+6FSEVNdw5alkWBuCqFmZEiUAGvwq0cougknnPpE4x4dUMhQj5hzJW0SIuvj92bLlXmlFpN2fB+iIYoLSaKEBgoeTumsrgOoAy4bGHiRsZTC8GFmu4mwDuQbFUI7o48GsjuINIlZiD5SK28AY9i6PuepyMK5lg6jonEDjX60LYXFWAKVWOjT8hNgK2Q1XygFtADDgKE6pk+PUpzZqcRRRn5UjpLy8AyFLy8hH3Fx3QL6M7FyCNCn4dtHf9mjerO7m/aCAPftFJoDEyGQPVKc195itAzJj8B4S+5/EG55m1gTWE42qpRO3s3OVtTuUNlJ0vQuJyDeelPWEKVWXKLsQbE2j3boKtzSWAzTecJU69WUlJ78v3WuINTJoyWm96c8gRct2TPRlOrw5Fri6QXgFm4/Tj1UpybGbugs1WN21MsW3aQjW1t9FLHm3G7lnBtxwZ7SpnHDBF3OfmhBlIRIymzWRYoon2sqyukJJkf5sBFoJFpy+u+bmZ9uxPCOAxiAoq4SMRDasxGnU4kwnyC/ZhHjJr7uSslOyy3LrdoIC0MEW40siIVVsQZRZNvbAODI7+2Eug/6aa9Wb6mIcJC9E/f9KukpQkzaZ4Fjs7H4Nhwh3OFeNdOGwY+3hQMxlXvtEY5kkdEXnPDSu00m7TdpfglLBN9bIfDizY8L3P0Ix4G1zVhFtiLQJl+qh1YudpCEF0LcCLK2NcCRFYgrHCT5muIJ87ZN3r3iqK7BUdC9UYCgumKxpfVH6J3lgJuxi12G2URUhKj6i29r4= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2025 13:10:48.2383 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4fbc9dd5-eb1d-4a05-70da-08dd349cdd02 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6734.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8499 X-Patchwork-Delegate: kuba@kernel.org From: Yevgeny Kliteynik When checking if the matcher size can be increased, check both match and action RTCs. Also, consider the increasing step - check that it won't cause the new matcher size to become unsupported. Additionally, since we're using '+ 1' for action RTC size yet again, define it as macro and use in all the required places. Signed-off-by: Yevgeny Kliteynik Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/steering/hws/bwc.c | 18 ++++++++++++++++-- .../mellanox/mlx5/core/steering/hws/matcher.c | 6 ++++-- .../mellanox/mlx5/core/steering/hws/matcher.h | 5 +++++ 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c index a8d886e92144..3dbd4efa21a2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/bwc.c @@ -468,8 +468,22 @@ hws_bwc_matcher_size_maxed_out(struct mlx5hws_bwc_matcher *bwc_matcher) { struct mlx5hws_cmd_query_caps *caps = bwc_matcher->matcher->tbl->ctx->caps; - return bwc_matcher->size_log + MLX5HWS_MATCHER_ASSURED_MAIN_TBL_DEPTH >= - caps->ste_alloc_log_max - 1; + /* check the match RTC size */ + if ((bwc_matcher->size_log + + MLX5HWS_MATCHER_ASSURED_MAIN_TBL_DEPTH + + MLX5HWS_BWC_MATCHER_SIZE_LOG_STEP) > + (caps->ste_alloc_log_max - 1)) + return true; + + /* check the action RTC size */ + if ((bwc_matcher->size_log + + MLX5HWS_BWC_MATCHER_SIZE_LOG_STEP + + ilog2(roundup_pow_of_two(bwc_matcher->matcher->action_ste.max_stes)) + + MLX5HWS_MATCHER_ACTION_RTC_UPDATE_MULT) > + (caps->ste_alloc_log_max - 1)) + return true; + + return false; } static bool diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c index 80157a29a076..b61864b32053 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.c @@ -289,7 +289,8 @@ static int hws_matcher_create_rtc(struct mlx5hws_matcher *matcher, * (2 to support writing new STEs for update rule)) */ ste->order = ilog2(roundup_pow_of_two(action_ste->max_stes)) + - attr->table.sz_row_log + 1; + attr->table.sz_row_log + + MLX5HWS_MATCHER_ACTION_RTC_UPDATE_MULT; rtc_attr.log_size = ste->order; rtc_attr.log_depth = 0; rtc_attr.update_index_mode = MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET; @@ -561,7 +562,8 @@ static int hws_matcher_bind_at(struct mlx5hws_matcher *matcher) pool_attr.flags = MLX5HWS_POOL_FLAGS_FOR_STE_ACTION_POOL; /* Pool size is similar to action RTC size */ pool_attr.alloc_log_sz = ilog2(roundup_pow_of_two(action_ste->max_stes)) + - matcher->attr.table.sz_row_log + 1; + matcher->attr.table.sz_row_log + + MLX5HWS_MATCHER_ACTION_RTC_UPDATE_MULT; hws_matcher_set_pool_attr(&pool_attr, matcher); action_ste->pool = mlx5hws_pool_create(ctx, &pool_attr); if (!action_ste->pool) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h index cff4ae854a79..020de70270c5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/matcher.h @@ -18,6 +18,11 @@ /* Required depth of the main large table */ #define MLX5HWS_MATCHER_ASSURED_MAIN_TBL_DEPTH 2 +/* Action RTC size multiplier that is required in order + * to support rule update for rules with action STEs. + */ +#define MLX5HWS_MATCHER_ACTION_RTC_UPDATE_MULT 1 + enum mlx5hws_matcher_offset { MLX5HWS_MATCHER_OFFSET_TAG_DW1 = 12, MLX5HWS_MATCHER_OFFSET_TAG_DW0 = 13,