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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Shahar Shitrit , Tariq Toukan Subject: [PATCH net-next 11/15] net/mlx5: Add support for 200Gbps per lane link modes Date: Mon, 3 Feb 2025 23:35:12 +0200 Message-ID: <20250203213516.227902-12-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F66:EE_|SJ1PR12MB6121:EE_ X-MS-Office365-Filtering-Correlation-Id: 16497318-e9d2-4e4a-2219-08dd449ae829 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: JrTpa39heH1R5UnVJAoxZJl05eguN66MbNlZDoGpF3FLGfOka82+yXalSo1vzJQLi8F8b/3jGKH/rL26caqu19OPriH94KsOryPy1eLq9f6YDZ3HR5X57ADQus4RfJEgnYlLpij6XdeHRw8wb1JAUPX624B18dT8KEMiYT709cYzcPv6+TIWwNdYxe1/vZnVPgIvSsIZwZl3HZd2sPK3EOlgGHaLfKpHR8qEesTHbn/nWQGe/q73NIFJYMlL5HxnkGEf59zvv3ADlYQyvpmQIMNibLOeVrK7CCidPlODCrGUiH92qqJQcbGQAPmjFwJ6P9kCez4h+e3FRTW0g9dNMAunfyWKDyJ8Metfiha3HWR/JVFEs2cZQkbcIEZuMYSOj0niLdt7cQyBJE+5l0WYpuOmjz3CEX/6+Lg5fzANd6+h3GSSpCGwFeyYhVMu6J7YaRuMTwUMvFaKsALn21mLph0QEVblRuxmzxDYPfStIlJsbq4b4JERf1ch1/Un//6lD3t4u8dEifqMEYLGo0zc+DLt8yWEe70VfLWyue1jf8C+6sa4LtM75p4menJveF6nJd5D8dUpckwyOXXzJ3hr5RSVaFUH36kHho2ygvD30GRwIzdX13aSOxsEcjxQz+xyCnvBJ9sQfzjRY8nCUytskKJFdc94sOs4HhMHtCzO4+7pIpdV7HNrEJgnI+6oiCNnn7vUe4GHfddcJPCgqhKMlvB4MdYiNrPlzJ9UWoL7/toBfYQhiqFzFPgizGsxowWlRj5W2Kle+k5ZemVOtKDkoA218Aa+KamOyCrwqnvylKNaV2FqdNfeL3L4fpCQEfnOhyWGBJz3fpszr5/fpkTlJy1n2SfRtYzdMWZhr7lRH+yQ9x928yq8xDD/67RLS+FGKRnRcExsAMCo9ueN/95PjZsJjI0tKiIh331PsLxW14xu9piP7/LzByjfpvR9aLB3rhtcuEzmPBEI/lJz7AKXVgNwjf1ieL/CYNzNwCIUGgeFMq0EijpnLMrIPsJuPl/2LOjMr1XuCzrlmtzr9tTaRqWbakjP8HQ2q0QhTBLMRmpz3UVsli4kTR+xOY/+7Dar+VHTrE0evMi9kIGwMmzkfNe628u8YGIhjrdb6ESTwpaUnTP80xtJj33Sx1NUWbvcD+/P0Jli/dUiWJLIeAjwqPez/xufJAVa8CiTCGjzwKui5abMUaFIoGFuDHKrpVz3sWyzRf9TLt+X3vL08g83c2Z8nHiC0igJco0Lwi6L0dtJ9p58s4bSsOkVtLXeXo8RGqATEC3zHoc0u5PI1gaQdApUVwmYor5Azgsjn8JKqJ3g62CsH5N5XeEyeXhuXTn0OXVLwApEredoiQXNUxhKmpYWrSKaL5CJjU3hCaJxIDgjhE7uDQAcW+6+drkhU12teNmrhjjL6iYvJQSWxvi4s5//AFtCLOGxKBjHExHZom3yHmy7GbJfRPhSJ1KNswwYcxG0EoNhy7WAC+xofNMDA5AO09als1iAAkrA1SnQr+M= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:37:06.5890 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 16497318-e9d2-4e4a-2219-08dd449ae829 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6121 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu This patch exposes new link modes using 200Gbps per lane, including 200G, 400G and 800G modes. Signed-off-by: Jianbo Liu Reviewed-by: Shahar Shitrit Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/en_ethtool.c | 21 +++++++++++++++++++ .../net/ethernet/mellanox/mlx5/core/port.c | 3 +++ include/linux/mlx5/port.h | 3 +++ 3 files changed, 27 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c index cae39198b4db..9c5fcc699515 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c @@ -237,6 +237,27 @@ void mlx5e_build_ptys2ethtool_map(void) ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT, ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT, ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT); + MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_200GAUI_1_200GBASE_CR1_KR1, ext, + ETHTOOL_LINK_MODE_200000baseCR_Full_BIT, + ETHTOOL_LINK_MODE_200000baseKR_Full_BIT, + ETHTOOL_LINK_MODE_200000baseDR_Full_BIT, + ETHTOOL_LINK_MODE_200000baseDR_2_Full_BIT, + ETHTOOL_LINK_MODE_200000baseSR_Full_BIT, + ETHTOOL_LINK_MODE_200000baseVR_Full_BIT); + MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_400GAUI_2_400GBASE_CR2_KR2, ext, + ETHTOOL_LINK_MODE_400000baseCR2_Full_BIT, + ETHTOOL_LINK_MODE_400000baseKR2_Full_BIT, + ETHTOOL_LINK_MODE_400000baseDR2_Full_BIT, + ETHTOOL_LINK_MODE_400000baseDR2_2_Full_BIT, + ETHTOOL_LINK_MODE_400000baseSR2_Full_BIT, + ETHTOOL_LINK_MODE_400000baseVR2_Full_BIT); + MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_800GAUI_4_800GBASE_CR4_KR4, ext, + ETHTOOL_LINK_MODE_800000baseCR4_Full_BIT, + ETHTOOL_LINK_MODE_800000baseKR4_Full_BIT, + ETHTOOL_LINK_MODE_800000baseDR4_Full_BIT, + ETHTOOL_LINK_MODE_800000baseDR4_2_Full_BIT, + ETHTOOL_LINK_MODE_800000baseSR4_Full_BIT, + ETHTOOL_LINK_MODE_800000baseVR4_Full_BIT); } static void mlx5e_ethtool_get_speed_arr(struct mlx5_core_dev *mdev, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/ethernet/mellanox/mlx5/core/port.c index 50931584132b..3995df064101 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c @@ -1105,6 +1105,9 @@ static const u32 mlx5e_ext_link_speed[MLX5E_EXT_LINK_MODES_NUMBER] = { [MLX5E_200GAUI_2_200GBASE_CR2_KR2] = 200000, [MLX5E_400GAUI_4_400GBASE_CR4_KR4] = 400000, [MLX5E_800GAUI_8_800GBASE_CR8_KR8] = 800000, + [MLX5E_200GAUI_1_200GBASE_CR1_KR1] = 200000, + [MLX5E_400GAUI_2_400GBASE_CR2_KR2] = 400000, + [MLX5E_800GAUI_4_800GBASE_CR4_KR4] = 800000, }; int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext, diff --git a/include/linux/mlx5/port.h b/include/linux/mlx5/port.h index e68d42b8ce65..fd625e0dd869 100644 --- a/include/linux/mlx5/port.h +++ b/include/linux/mlx5/port.h @@ -115,9 +115,12 @@ enum mlx5e_ext_link_mode { MLX5E_100GAUI_1_100GBASE_CR_KR = 11, MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12, MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13, + MLX5E_200GAUI_1_200GBASE_CR1_KR1 = 14, MLX5E_400GAUI_8_400GBASE_CR8 = 15, MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16, + MLX5E_400GAUI_2_400GBASE_CR2_KR2 = 17, MLX5E_800GAUI_8_800GBASE_CR8_KR8 = 19, + MLX5E_800GAUI_4_800GBASE_CR4_KR4 = 20, MLX5E_EXT_LINK_MODES_NUMBER, };