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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 02/15] net/mlx5: Change parameters for PTP internal functions Date: Mon, 3 Feb 2025 23:35:03 +0200 Message-ID: <20250203213516.227902-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F61:EE_|CYYPR12MB8653:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f5781b1-3d05-4849-3b69-08dd449ad2f5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: 5DpSzFAJAed31Ak9xKFqYSrjJ87/AQhLtUnWmPeVXm172PvR6PO4p9bLX5614d/IvNMiC5b4mN2BzLBZYBBe13V5939+mgNNtP9sIOPnLWYie+tuKX+khh09LeJdtINX79izKzG6RLercd34Q8RvYQdE65BnXrNvVvlGdjiwoOj/PS0TRVg7b5uf5usjNt23DGTO+f3px+8QzZEadxMwsYlWO34Q7NUJBaY5Pb3dCdm0B+Vz1Qir9w/nycYCSXNiKNSHiYnTWPxKv9HpJIbxVuj8gACCnfIUOgCwbhdGummlOs7nXP1uIMX/Mv3TcC+AUF1muH4MVO4Gj6CrV6Lx9uTk/A0NeSp8lzZrXW8O1wFjkGeK7yI74jIEdgLhI/syWdst25Gacc5ZOrbDd7VpzeOSsJSMR9P00eGV1Lw4cJzGdOEy1co6cVu5Oh4zgpf95fcEJkLt1p7HKnfbFKbp7OG8ukSGptEauJbvI+hnXS/Img1JloEW7qnHWoSXdtPYbbJaBvgproZp24lvA0M/FqSpKO/GeiQlxgb/fgKPNY87cDAQM+mxuAmFkz13yr50kiTfX4lGpOU0QyBUXoK+Qd1MQZntXe94ZqZUePSHCq2FjKyVo14V+AYnziFkB9HgPN/UaJ+jq37ojpKxHSiZKfLl39NZ84FmWQq5+h517E6QmZKoemQz6mzwd/Bf9lDDvrsHfGTdNB5m4n8ml0ydQeRCYkOig+58x93UuOCexfZU65kYAPLrUqR1LJhgHcJU0IOqGCf5aUoe7IisK+hhR9HKFxpD2s5p5OzkESXRcKdoIbJU/LHv1ABJH9wMQrLE/OxgBCg7WDyUWQjkMT4GJqwNtbqbugEtZmpiUZimM37+CqkSM82w2k5ObnqRue+2elh0kZqABTYU7FHSIy9gQAPjmRWnLselcWwbbPQqWSOv6+Oh+kGtzphZ7MWmP1FOHnc69sl/bzn79E7BP1pLVNvPSF9saq7Lcsu/gXQrZhzqPvacwTGzdTlLxFc5ub/eRGlxkHDsQWVUIu1NHx3uE8Q3Db5vGeXW32lzW7EQ8ko6h2jRMhHrBa0+HUJbF20oemW4LAAmyhTsVifbHrwEAEJJCiAkQp/rzNoGk4J6miNEdzyUfm6a+pMckbpO+g9ck7VyA+D3fTd+vwT+G5hjTgJPUedmeY0v3raLnqkdlFBKKS9ecfxM1TgttIwA+ukHR3DDm+jL0mnaQC4II4rxdT6qZdfQ8siER22zrcKWfd7gLp3aqpSCs8p7uYuogl6RHWaw5lx+xaNhAJUvMFiAi1qjtqB0nr29hiaxMPoWQPvqhPIDSe/bsMgk7abdDETRugKyoD8f6nr8kxGqoe2MDXEA+DqrPDqOkzi2waBNhi7Ai/kGqSRFTebb3hZYBp+cNG+FGSJ0RGA0tz5vwa7zPFEFQpmkiUMAKJ5bdBsqMHG1k3yoV3iIRD2+9n7IT3UP/4tR7jH5E1ZgR9+gsadHGwqG25e9IU8y8uldRc0DpR8= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:31.0011 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f5781b1-3d05-4849-3b69-08dd449ad2f5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F61.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8653 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu In later patch, the mlx5_clock will be allocated dynamically, its address can be obtained from mlx5_core_dev struct, but mdev can't be obtained from mlx5_clock because it can be shared by multiple interfaces. So change the parameter for such internal functions, only mdev is passed down from the callers. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index eaf343756026..e7e4bdba02a3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -878,10 +878,8 @@ static int mlx5_query_mtpps_pin_mode(struct mlx5_core_dev *mdev, u8 pin, mtpps_size, MLX5_REG_MTPPS, 0, 0); } -static int mlx5_get_pps_pin_mode(struct mlx5_clock *clock, u8 pin) +static int mlx5_get_pps_pin_mode(struct mlx5_core_dev *mdev, u8 pin) { - struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock); - u32 out[MLX5_ST_SZ_DW(mtpps_reg)] = {}; u8 mode; int err; @@ -900,8 +898,9 @@ static int mlx5_get_pps_pin_mode(struct mlx5_clock *clock, u8 pin) return PTP_PF_NONE; } -static void mlx5_init_pin_config(struct mlx5_clock *clock) +static void mlx5_init_pin_config(struct mlx5_core_dev *mdev) { + struct mlx5_clock *clock = &mdev->clock; int i; if (!clock->ptp_info.n_pins) @@ -922,7 +921,7 @@ static void mlx5_init_pin_config(struct mlx5_clock *clock) sizeof(clock->ptp_info.pin_config[i].name), "mlx5_pps%d", i); clock->ptp_info.pin_config[i].index = i; - clock->ptp_info.pin_config[i].func = mlx5_get_pps_pin_mode(clock, i); + clock->ptp_info.pin_config[i].func = mlx5_get_pps_pin_mode(mdev, i); clock->ptp_info.pin_config[i].chan = 0; } } @@ -1041,10 +1040,10 @@ static void mlx5_timecounter_init(struct mlx5_core_dev *mdev) ktime_to_ns(ktime_get_real())); } -static void mlx5_init_overflow_period(struct mlx5_clock *clock) +static void mlx5_init_overflow_period(struct mlx5_core_dev *mdev) { - struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock); struct mlx5_ib_clock_info *clock_info = mdev->clock_info; + struct mlx5_clock *clock = &mdev->clock; struct mlx5_timer *timer = &clock->timer; u64 overflow_cycles; u64 frac = 0; @@ -1135,7 +1134,7 @@ static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) mlx5_timecounter_init(mdev); mlx5_init_clock_info(mdev); - mlx5_init_overflow_period(clock); + mlx5_init_overflow_period(mdev); if (mlx5_real_time_mode(mdev)) { struct timespec64 ts; @@ -1147,13 +1146,11 @@ static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) static void mlx5_init_pps(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = &mdev->clock; - if (!MLX5_PPS_CAP(mdev)) return; mlx5_get_pps_caps(mdev); - mlx5_init_pin_config(clock); + mlx5_init_pin_config(mdev); } void mlx5_init_clock(struct mlx5_core_dev *mdev)