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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 03/15] net/mlx5: Add init and destruction functions for a single HW clock Date: Mon, 3 Feb 2025 23:35:04 +0200 Message-ID: <20250203213516.227902-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002322:EE_|CY8PR12MB7490:EE_ X-MS-Office365-Filtering-Correlation-Id: a55a95c1-ef80-4f07-9d59-08dd449ad860 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: UvB0/Em16Mn4boAsF1qn+gPwUYxchuAWZPMTrvoHCQB3aRHQ8HVyG8fuPnl4Pb67FtWvDD4ffV7gA3HaHp0G2nk+x9q0Cy1kdHJyKJlyD5bpX3WLNscoyND5J0ewmgrykpctMmn1S4KceqOZ9G4+/Sj+fyWCVxO9unYUjSgICAsJxXls+dn2Ju+QS/sNv4XlVSknpA2YmDkZipn1VuJvTFjO1WzhevrfNJ9EP7dcK2/SBN2F4LzEoQDNg7D6hPDSEevS8VtBXo0M5hO+Tsulb5lfxWArnyY+mSq/89lXcdm5+v1HRb5kgOpe6eWfDW63lTY6CoSPMuwJ4Cxby5sgznMcVuPNLRVXkuO6rJh0ISCPfY4+cWSsQndzrQQ0Kwg5wr2S+zLSho3K32tI2isD+/UAe+/foz9V3GhhiJLuGnx9ULiD5u6HwA1vOytYWyur+rfJhRq7Uns3UyAafjh+F9Y1cf06Yg/I2R6X3vbARM39fZ1QcSTj4gw/2upoBhEC1Qtt0jdfba5W9M2F/cLF6d/bYlD343LLDEeTlJ27zkkJBAEOeh7w7lBQAbYbJY20QGqJYdrhIlZID/To2OhYzD5Y7ywCyQNZdwOn/H//toFxC8Q5u4vmorazGAv+6i7ld0XJORWCNoTmhtdGHvsbz+AfkFTXajtf2yLwVRSuZ0fxP62krM+GSsEXFQafXYzBMaDRR0ZKiKI1EB4pgiM9Fq63xlIpupTXUa2Pdi9/k+TfaAQkPCUfCJL4zKpXbHOhE/ah652vXF9DwakTMgFG1/npogr8epUwaznoXSxZ3yOfqR4pdoW454XA+v+61iPri3sb8E+eALA8trBLS8elZACMzswq5crK/iCBTeiq6dzsmO1Kq0sTrAjS3AALbF/6xhQKMl/djFMZtgPicf5fUEqAtYt8fvgpeRJa1gJtGsBIsk91gMI0p4TFKRvgsqPql5BPMmEz8k3UH9Qpn8lkGhyv6l80z3ocTihEHsVDXb4amA9j5Ufk3dv0eVAbKvpcjDtxRWqb0DyOacbAJLc4Opl2ZZMZRmYPNabAqmp9WOiolPiyuauzQ3Dj4aWMvAhWrLYn3Lvtx4faM8rhDgJQYmQg5PaR4J2Lx+e7Gn/NvbNSeu+d2lMOnkkY9mHeCLP6/VwqaFw/ZU1stRgUONJDB0XPr4MfHYVa79RJ11KoYDO2jlhKKzlGQyQAh1WIPicoWw84DaVBBV7mb1nLD3iP8sPBBuTl1zktc+PUOGrGuSeF7TPA1bvB7QYarrSt7MiawXLIRye6kLqzcIggbDcve4QWBWPHK05plasG7pFDEKWVths5pgdhj9OgDHQbmqXZyGejcTas2O7aBxBjuvigj8CFaEkrVmAVEf80jkXaazbcBjoffhfhboXPgufsn4OJiXcGK0wT83pWxkGrMjrrojnqnETR7LiXE3fNtE8BAepp9aq9LXhpz3E2bahEQ6rE48w/w39/+qvayGYuQk7U2BcnbTESHVPZZqbd4V75xvQ= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:40.2028 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a55a95c1-ef80-4f07-9d59-08dd449ad860 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002322.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7490 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu Move hardware clock initialization and destruction to the functions, which will be used for dynamically allocated clock. Such clock is shared by all the devices if the queried clock identities are same. The out_work is for PPS out event, which can't be triggered when clock is shared, so INIT_WORK is not moved to the initialization function. Besides, we still need to register notifier for each device. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 48 ++++++++++++------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index e7e4bdba02a3..cc0a491bf617 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -1153,17 +1153,11 @@ static void mlx5_init_pps(struct mlx5_core_dev *mdev) mlx5_init_pin_config(mdev); } -void mlx5_init_clock(struct mlx5_core_dev *mdev) +static void mlx5_init_clock_dev(struct mlx5_core_dev *mdev) { struct mlx5_clock *clock = &mdev->clock; - if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) { - mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting HW clock init\n"); - return; - } - seqlock_init(&clock->lock); - INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out); /* Initialize the device clock */ mlx5_init_timer_clock(mdev); @@ -1179,28 +1173,19 @@ void mlx5_init_clock(struct mlx5_core_dev *mdev) clock->ptp = NULL; } - MLX5_NB_INIT(&clock->pps_nb, mlx5_pps_event, PPS_EVENT); - mlx5_eq_notifier_register(mdev, &clock->pps_nb); - if (clock->ptp) ptp_schedule_worker(clock->ptp, 0); } -void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) +static void mlx5_destroy_clock_dev(struct mlx5_core_dev *mdev) { struct mlx5_clock *clock = &mdev->clock; - if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) - return; - - mlx5_eq_notifier_unregister(mdev, &clock->pps_nb); if (clock->ptp) { ptp_clock_unregister(clock->ptp); clock->ptp = NULL; } - cancel_work_sync(&clock->pps_info.out_work); - if (mdev->clock_info) { free_page((unsigned long)mdev->clock_info); mdev->clock_info = NULL; @@ -1208,3 +1193,32 @@ void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) kfree(clock->ptp_info.pin_config); } + +void mlx5_init_clock(struct mlx5_core_dev *mdev) +{ + struct mlx5_clock *clock = &mdev->clock; + + if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) { + mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting HW clock init\n"); + return; + } + + mlx5_init_clock_dev(mdev); + + INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out); + MLX5_NB_INIT(&clock->pps_nb, mlx5_pps_event, PPS_EVENT); + mlx5_eq_notifier_register(mdev, &clock->pps_nb); +} + +void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) +{ + struct mlx5_clock *clock = &mdev->clock; + + if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) + return; + + mlx5_eq_notifier_unregister(mdev, &clock->pps_nb); + cancel_work_sync(&clock->pps_info.out_work); + + mlx5_destroy_clock_dev(mdev); +}