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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 04/15] net/mlx5: Add API to get mlx5_core_dev from mlx5_clock Date: Mon, 3 Feb 2025 23:35:05 +0200 Message-ID: <20250203213516.227902-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002324:EE_|MN0PR12MB6224:EE_ X-MS-Office365-Filtering-Correlation-Id: 177102d8-5815-476f-9277-08dd449ada2b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: kKa75SBSaYsNdPQ44cT9OWw4Iyf/Hf/t7n2IsbPXgDdYmKfO2q9823bOnQ++FI43hHyN8pj5tUOC++mD80A3ns1yKtj1q5eNF5rYc+DjbNSxR8PM/woOytV2RxWIeFHCcNyW3h1vlyhovhGoS6ffYsxTDMbH3wSTu2VxazFRRS5EIXLMUfvRDdKTiIOLHO7wzoSma8U3Um/qjA/pbkbTGs4XtcLvN4ofdfQ+NRpbTDUAQ7bivCVEnBlMefhBrqKVEj0S14EX3oVUJn/4qKJZ28waktDBvWh8hIf6LC4yC32ahBYv9FNfdVLfDaWmjHklM14dTwa7e2Idcb4nx75tll3PhPBJWQ6iTK+b9cQ+4QpGcp4mVtYWiyary+VExXuasuS0NgG/uUMwNYMSnc8/nPozdBC/YA8pvMUw3K7/IopBCqB6pvkcLVMgR3t0aKyrQMi6zslPnMXMisGzAZfcIrb5uYx9ENYwCPRy1lO2kJ7gxcljzaw55F64+KmN+ukuGmBU7UXkZasqleH37IMMJjTwqgBOuT9pOsU1l8rz+ekGEVwx+RuiDj5BEOSinNVnaE8sKO3cn20CsOlqJVTtajNePJsUC8R31JHKSW6IvHvoziu5DZfHGczUwHNu2JY/+Zib5aPnmOe40/CVwymU6EMFRVcQG26V9EGpbpgy84cH8APJZ+ozbpXc0q1KKMSBcE5s/c4H0B+ZTyrG7RdwSW2uKIuT11oVU8u/DqCBzSbnnW8zKp9fH/0YBzI58vVut6LicZq3vqSt/ZrtQvsUvfIFACL1ow5eQYFIEmrNH3oJdHlhLDmbv+I8rMkUo7zxVH9AGf8jE7+tOwmrgQBtCtex7XVg+nO0n0nUizwGOgYxftM4mVB+w+WR68ZeH81dmJ4PCRaYto+vSP2JIuxwjafqoX8cA19Th6BoWvzl2OD8v73LG1aZ8iTcCheHzVs14MlYAzyYOci7g+0ln+we4QCPkZ6Si9vBUa8xg/OyZ6MHrsWfE0Kow6A8iJK9kk85PQWbyc2RnW/VX0zIh2eCqzHMvyE5/lCb01zJ+k1LwgSLrkpyd/wTITYFdFTqRF10OeW3twBFHBJEeDB9dUqNMbLjBdmJ3/Ji6vA7Q1bQs6qej0OPNfKTYvU0R7SkJZNeMFTOUPzdpH/ZRjcyF+xI+wp23lyfH6uNnZ77avYEaYQ7OdrJta/sXLMLAJA/3IWi1Wyd16Zp44553qEVazzkY/6uNKC6gucVpcSm/KNyHYS1c9BagIO5wZp9tVDEEc2E7TbUeE50Ab0ZMdqrqwzNPC9/qGMwX/bech3b1/Q4dAs7OcGLItv/d0OO2Z4kFvs4p2eqjGvdDWygHFPOvATmfYnppCaa8/ypG0B6npF3pO/SVSE9FUQVG7yUjkhLrJ5xN7x6ByzoGafk4LE20svmaTs9SM5X+pX2JMdOGbdGNWOTAAlVY1xIBKAqMjV0mCbNzs7IdzSCptKKqI8QmVovRRaIOztl/9meas2tSNS29us= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:43.1950 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 177102d8-5815-476f-9277-08dd449ada2b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002324.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6224 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu The mdev is calculated directly from mlx5_clock, as it's one of the fields in mlx5_core_dev. Move to a function so it can be easily changed in next patch. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 35 ++++++++++--------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index cc0a491bf617..b2c88050ba36 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -77,6 +77,11 @@ enum { MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX = 200000, }; +static struct mlx5_core_dev *mlx5_clock_mdev_get(struct mlx5_clock *clock) +{ + return container_of(clock, struct mlx5_core_dev, clock); +} + static bool mlx5_real_time_mode(struct mlx5_core_dev *mdev) { return (mlx5_is_real_time_rq(mdev) || mlx5_is_real_time_sq(mdev)); @@ -131,7 +136,7 @@ static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp) struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); struct mlx5_core_dev *mdev; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); return mlx5_clock_getmaxphase(mdev); } @@ -226,7 +231,7 @@ static int mlx5_ptp_getcrosststamp(struct ptp_clock_info *ptp, struct system_time_snapshot history_begin = {0}; struct mlx5_core_dev *mdev; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); if (!mlx5_is_ptm_source_time_available(mdev)) return -EBUSY; @@ -268,8 +273,7 @@ static u64 read_internal_timer(const struct cyclecounter *cc) { struct mlx5_timer *timer = container_of(cc, struct mlx5_timer, cycles); struct mlx5_clock *clock = container_of(timer, struct mlx5_clock, timer); - struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, - clock); + struct mlx5_core_dev *mdev = mlx5_clock_mdev_get(clock); return mlx5_read_time(mdev, NULL, false) & cc->mask; } @@ -304,8 +308,7 @@ static void mlx5_pps_out(struct work_struct *work) out_work); struct mlx5_clock *clock = container_of(pps_info, struct mlx5_clock, pps_info); - struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, - clock); + struct mlx5_core_dev *mdev = mlx5_clock_mdev_get(clock); u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; unsigned long flags; int i; @@ -335,7 +338,7 @@ static long mlx5_timestamp_overflow(struct ptp_clock_info *ptp_info) unsigned long flags; clock = container_of(ptp_info, struct mlx5_clock, ptp_info); - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); timer = &clock->timer; if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) @@ -392,7 +395,7 @@ static int mlx5_ptp_settime(struct ptp_clock_info *ptp, const struct timespec64 struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); struct mlx5_core_dev *mdev; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); return mlx5_clock_settime(mdev, clock, ts); } @@ -416,7 +419,7 @@ static int mlx5_ptp_gettimex(struct ptp_clock_info *ptp, struct timespec64 *ts, struct mlx5_core_dev *mdev; u64 cycles, ns; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); if (mlx5_real_time_mode(mdev)) { *ts = mlx5_ptp_gettimex_real_time(mdev, sts); goto out; @@ -457,7 +460,7 @@ static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) struct mlx5_core_dev *mdev; unsigned long flags; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); if (mlx5_modify_mtutc_allowed(mdev)) { int err = mlx5_ptp_adjtime_real_time(mdev, delta); @@ -479,7 +482,7 @@ static int mlx5_ptp_adjphase(struct ptp_clock_info *ptp, s32 delta) struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); struct mlx5_core_dev *mdev; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); return mlx5_ptp_adjtime_real_time(mdev, delta); } @@ -512,7 +515,7 @@ static int mlx5_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) unsigned long flags; u32 mult; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); if (mlx5_modify_mtutc_allowed(mdev)) { int err = mlx5_ptp_freq_adj_real_time(mdev, scaled_ppm); @@ -539,8 +542,7 @@ static int mlx5_extts_configure(struct ptp_clock_info *ptp, { struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); - struct mlx5_core_dev *mdev = - container_of(clock, struct mlx5_core_dev, clock); + struct mlx5_core_dev *mdev = mlx5_clock_mdev_get(clock); u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; u32 field_select = 0; u8 pin_mode = 0; @@ -724,8 +726,7 @@ static int mlx5_perout_configure(struct ptp_clock_info *ptp, { struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); - struct mlx5_core_dev *mdev = - container_of(clock, struct mlx5_core_dev, clock); + struct mlx5_core_dev *mdev = mlx5_clock_mdev_get(clock); bool rt_mode = mlx5_real_time_mode(mdev); u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; u32 out_pulse_duration_ns = 0; @@ -987,7 +988,7 @@ static int mlx5_pps_event(struct notifier_block *nb, unsigned long flags; u64 ns; - mdev = container_of(clock, struct mlx5_core_dev, clock); + mdev = mlx5_clock_mdev_get(clock); switch (clock->ptp_info.pin_config[pin].func) { case PTP_PF_EXTTS: