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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Jianbo Liu , Moshe Shemesh , Leon Romanovsky , Mark Bloch , Carolina Jubran , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 07/15] net/mlx5: Move PPS notifier and out_work to clock_state Date: Mon, 3 Feb 2025 23:35:08 +0200 Message-ID: <20250203213516.227902-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250203213516.227902-1-tariqt@nvidia.com> References: <20250203213516.227902-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003F68:EE_|CH3PR12MB8510:EE_ X-MS-Office365-Filtering-Correlation-Id: b8f4e1a4-20ef-4680-ce89-08dd449adec7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: C576PNFQlknEpEbSKaDKWLkKMwR2MWORHQ3Woor8vnd/IX4f7tGuZ2xFUA9H2tGNqFukxgCC7S8BKQ5/WwI7WYn5Jk7VkMpdH7EIUYKttNCLVho+1AhXNjera0B9qPoWIysl9bupXEmZ3zR40cAToiZTdbQzKXZxlQ6FNRfxvOcp3xzw4ztten3CWlhAzTLYG8NXxbb3umNNKKX9qkXcw4hQCPH+vAMUtaU01X0VOk9lBo+Ew3oUwAMImZF90q4sssKPe6BRbPNApYktCgn0Td836gwLBxrWnE2lhKMDzRCfY+RfazYOYHKAJWToucrOyxburPG1ek8kFq/cR2ehs057joKknMb/7DsSu/ROAdx9wBot7uKtEHoNf2F/oyQR/n7YpQFQ2w2oMa0ofTQhw73E8huvWMeIvhgO9gQGMJIYTouSFf2gqW0dKOqAR5kqmtSu9wrlDIHanTk3V8ocmAAit1TprduP2J5YN9DNbCeKvQFVUQV8Uv4461yw8m/H5Ky2bQd1DHHC6pFaar6NbUc++FfnaYKBXs31DVlx0lWlI2//D3xNRGDuBEtb6RF0cNmDAHaA+lCuMZjcYT4sofIwzVtpTaX/kv3J2y5Djlo9HDvegXSldjhITrOf1xzO9Tu67lnnRPgZiRxsFlE3OBFUMbbv4WTDDMYzkubSot/6ug3g78HqjItfxTuotSR/p3Tf7gTwE7DmhuHkKf779Tqd+MQJ9zhSJ48kTAMtqGfkJkr0unLRHLlzXkyqRuFNWhUq0yX0BTfNbNiJUseCApEpWmXV5cc7O3bcbKc/xRsV/qIlvGee5s1zbz+aZMUCRyTwl3zOV7OpF+V2WbjrHv6gVs1K/idu0KSV6z4vg2JuSc/CIjVkpINf6qvRjbcFjGCul35TydNDbbghA4DjBrHVz+8fPDvGAVPQdTvBWKDg3cTi9E/2Ybitq9jKl7DjxK+WZAZX918y0DoK1Zk5fpX5GeFuKVDmzdV0K1O3QuwtGizm3R82KnHNEiYA5P5gk2vgPRCKPFtv6stbMELOGRqIImy5hYwbjb/hOeoueNFk+4ELaLXNCc4eLjS1rri4sNIGAn4f0Kpf4jpD5sbEH/4dkpgKo/627ngHscV5wLSDBUIlP5Ln+t8RNRL3Tevr6GxqN6WcCcla3tIG/ooEepzHXF8YUqsUslSpw1fmY5XH0xz78eQlASV921pwKR2tM8QAW8oXeZmvlBIC/o2gPIMK4j1Isg7NGGB3cUrG0VM9EqBoFOYooIHdrK+vvHQkq3aFccOf3vIZOd7vT71NpiKKsr2YAK05ahoEvxJ4S6gcs5FK4cNgOYCu2iwj6popMHZ0PjaGwTavEhV6ltipNEva7lUXQxpvi/+lTftXrUCEgj1Mu352OJzwZcGrc9iedVqfXwyFkOVdryTiV7ds8JfGu9Rxxn17ykbCWLdXfBLsRjQbkOIpsrp+/xFP+F2s0foWlzuqBWFbhYtltRcETKAHVuVEu/jDNxh3KreP8Zc= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2025 21:36:50.8361 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8f4e1a4-20ef-4680-ce89-08dd449adec7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F68.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8510 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu The PPS notifier is currently in mlx5_clock, and mlx5_clock can be shared in later patch, so the notifier should be registered for each device to avoid any event miss. Besides, the out_work is scheduled by PPS out event which is triggered only when the device is in free running mode. So, both are moved to mlx5_core_dev's clock_state. Signed-off-by: Jianbo Liu Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 37 +++++++++---------- .../ethernet/mellanox/mlx5/core/lib/clock.h | 2 - 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 7e5882ea19e0..2586b0788b40 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -80,7 +80,10 @@ enum { }; struct mlx5_clock_dev_state { + struct mlx5_core_dev *mdev; struct mlx5_devcom_comp_dev *compdev; + struct mlx5_nb pps_nb; + struct work_struct out_work; }; struct mlx5_clock_priv { @@ -336,11 +339,10 @@ static void mlx5_update_clock_info_page(struct mlx5_core_dev *mdev) static void mlx5_pps_out(struct work_struct *work) { - struct mlx5_pps *pps_info = container_of(work, struct mlx5_pps, - out_work); - struct mlx5_clock *clock = container_of(pps_info, struct mlx5_clock, - pps_info); - struct mlx5_core_dev *mdev = mlx5_clock_mdev_get(clock); + struct mlx5_clock_dev_state *clock_state = container_of(work, struct mlx5_clock_dev_state, + out_work); + struct mlx5_core_dev *mdev = clock_state->mdev; + struct mlx5_clock *clock = mdev->clock; u32 in[MLX5_ST_SZ_DW(mtpps_reg)] = {0}; unsigned long flags; int i; @@ -1012,16 +1014,16 @@ static u64 perout_conf_next_event_timer(struct mlx5_core_dev *mdev, static int mlx5_pps_event(struct notifier_block *nb, unsigned long type, void *data) { - struct mlx5_clock *clock = mlx5_nb_cof(nb, struct mlx5_clock, pps_nb); + struct mlx5_clock_dev_state *clock_state = mlx5_nb_cof(nb, struct mlx5_clock_dev_state, + pps_nb); + struct mlx5_core_dev *mdev = clock_state->mdev; + struct mlx5_clock *clock = mdev->clock; struct ptp_clock_event ptp_event; struct mlx5_eqe *eqe = data; int pin = eqe->data.pps.pin; - struct mlx5_core_dev *mdev; unsigned long flags; u64 ns; - mdev = mlx5_clock_mdev_get(clock); - switch (clock->ptp_info.pin_config[pin].func) { case PTP_PF_EXTTS: ptp_event.index = pin; @@ -1045,7 +1047,7 @@ static int mlx5_pps_event(struct notifier_block *nb, write_seqlock_irqsave(&clock->lock, flags); clock->pps_info.start[pin] = ns; write_sequnlock_irqrestore(&clock->lock, flags); - schedule_work(&clock->pps_info.out_work); + schedule_work(&clock_state->out_work); break; default: mlx5_core_err(mdev, " Unhandled clock PPS event, func %d\n", @@ -1271,7 +1273,6 @@ int mlx5_init_clock(struct mlx5_core_dev *mdev) { u8 identity[MLX5_RT_CLOCK_IDENTITY_SIZE]; struct mlx5_clock_dev_state *clock_state; - struct mlx5_clock *clock; u64 key; int err; @@ -1284,6 +1285,7 @@ int mlx5_init_clock(struct mlx5_core_dev *mdev) clock_state = kzalloc(sizeof(*clock_state), GFP_KERNEL); if (!clock_state) return -ENOMEM; + clock_state->mdev = mdev; mdev->clock_state = clock_state; if (MLX5_CAP_MCAM_REG3(mdev, mrtcq) && mlx5_real_time_mode(mdev)) { @@ -1301,24 +1303,21 @@ int mlx5_init_clock(struct mlx5_core_dev *mdev) mdev->clock_state = NULL; return err; } - clock = mdev->clock; - INIT_WORK(&clock->pps_info.out_work, mlx5_pps_out); - MLX5_NB_INIT(&clock->pps_nb, mlx5_pps_event, PPS_EVENT); - mlx5_eq_notifier_register(mdev, &clock->pps_nb); + INIT_WORK(&mdev->clock_state->out_work, mlx5_pps_out); + MLX5_NB_INIT(&mdev->clock_state->pps_nb, mlx5_pps_event, PPS_EVENT); + mlx5_eq_notifier_register(mdev, &mdev->clock_state->pps_nb); return 0; } void mlx5_cleanup_clock(struct mlx5_core_dev *mdev) { - struct mlx5_clock *clock = mdev->clock; - if (!MLX5_CAP_GEN(mdev, device_frequency_khz)) return; - mlx5_eq_notifier_unregister(mdev, &clock->pps_nb); - cancel_work_sync(&clock->pps_info.out_work); + mlx5_eq_notifier_unregister(mdev, &mdev->clock_state->pps_nb); + cancel_work_sync(&mdev->clock_state->out_work); mlx5_clock_free(mdev); mlx5_shared_clock_unregister(mdev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h index eca1dd9039be..3c5fee246582 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h @@ -38,7 +38,6 @@ #define MAX_PIN_NUM 8 struct mlx5_pps { u8 pin_caps[MAX_PIN_NUM]; - struct work_struct out_work; u64 start[MAX_PIN_NUM]; u8 enabled; u64 min_npps_period; @@ -53,7 +52,6 @@ struct mlx5_timer { }; struct mlx5_clock { - struct mlx5_nb pps_nb; seqlock_t lock; struct hwtstamp_config hwtstamp_config; struct ptp_clock *ptp;