From patchwork Wed Feb 5 15:32:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steffen Trumtrar X-Patchwork-Id: 13961375 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A3F81DA628 for ; Wed, 5 Feb 2025 15:32:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769576; cv=none; b=DMJqAVyc40rCVBuavqR2IJxayG85MvEGtvhXidXmBRDdHZcygAmtfb0HJs7HaP6T9vPulkneIx1/shBh1g4LUFXtf6uO7P8guHTb97be9fnmwcx9wKHDaWIB7elR5+WlWy4arB54N5VnEJBIC3kveqH/r3x+X2SIfkP7BifBoYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738769576; c=relaxed/simple; bh=La5zx3Qvv38baoWL9CvoEcR77JLw7HpuWy4xOz2jhoU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cK8KWMQMNiPKPoW/eZKwHRtbtEDLrt2B0GXu37YgUJ7OaQkqDvGGNeW98IpXJh8Azd4cRqeVo5TgqQ0P2CLRtHd1nhGYTJGTWtj5nMr4YVanoyL6rh6VvPijoNTLQEI7mnKHynyA2Z8eGQbXu8vrHuAMxvJHdOFpOCr3UIjfqUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from ptz.office.stw.pengutronix.de ([2a0a:edc0:0:900:1d::77] helo=ratatoskr.trumtrar.info) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1tfhOL-0005Jb-Mc; Wed, 05 Feb 2025 16:32:41 +0100 From: Steffen Trumtrar Date: Wed, 05 Feb 2025 16:32:25 +0100 Subject: [PATCH v4 4/6] arm64: dts: agilex5: add gmac nodes Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20250205-v6-12-topic-socfpga-agilex5-v4-4-ebf070e2075f@pengutronix.de> References: <20250205-v6-12-topic-socfpga-agilex5-v4-0-ebf070e2075f@pengutronix.de> In-Reply-To: <20250205-v6-12-topic-socfpga-agilex5-v4-0-ebf070e2075f@pengutronix.de> To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen Cc: kernel@pengutronix.de, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Steffen Trumtrar X-Mailer: b4 0.14.2 X-SA-Exim-Connect-IP: 2a0a:edc0:0:900:1d::77 X-SA-Exim-Mail-From: s.trumtrar@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: netdev@vger.kernel.org The Agilex5 provides three Synopsys XGMAC ethernet cores, that can be used to transmit and receive data at 10M/100M/1G/2.5G over ethernet connections and enables support for Time Sensitive Networking (TSN) applications. Signed-off-by: Steffen Trumtrar --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 90 ++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 51c6e19e40b843adbdb58cfa987878d5b0bbb652..6a9f76cfdf8ea51c4f3498e9f20ef143cb3dae5a 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -141,6 +141,96 @@ soc: soc@0 { device_type = "soc"; interrupt-parent = <&intc>; + gmac0: ethernet@10810000 { + compatible = "altr,socfpga-stmmac-agilex5", + "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg = <0x10810000 0x3500>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "macirq"; + max-frame-size = <3800>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <32768>; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC0_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + snps,axi-config = <&stmmac_axi_emac0_setup>; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + status = "disabled"; + + stmmac_axi_emac0_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + }; + + gmac1: ethernet@10820000 { + compatible = "altr,socfpga-stmmac-agilex5", + "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg = <0x10820000 0x3500>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "macirq"; + max-frame-size = <3800>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <32768>; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC1_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + snps,axi-config = <&stmmac_axi_emac1_setup>; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + status = "disabled"; + + stmmac_axi_emac1_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + }; + + gmac2: ethernet@10830000 { + compatible = "altr,socfpga-stmmac-agilex5", + "altr,socfpga-stmmac-a10-s10", + "snps,dwxgmac-2.10", + "snps,dwxgmac"; + reg = <0x10830000 0x3500>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "macirq"; + max-frame-size = <3800>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <64>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <32768>; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "ahb"; + clocks = <&clkmgr AGILEX5_EMAC2_CLK>, + <&clkmgr AGILEX5_EMAC_PTP_CLK>; + clock-names = "stmmaceth", "ptp_ref"; + snps,axi-config = <&stmmac_axi_emac2_setup>; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + status = "disabled"; + + stmmac_axi_emac2_setup: stmmac-axi-config { + snps,wr_osr_lmt = <31>; + snps,rd_osr_lmt = <31>; + snps,blen = <0 0 0 32 16 8 4>; + }; + }; + clkmgr: clock-controller@10d10000 { compatible = "intel,agilex5-clkmgr"; reg = <0x10d10000 0x1000>;