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Wed, 5 Feb 2025 09:20:11 -0600 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v10 10/26] cxl: modify dpa setup process for supporting type2 Date: Wed, 5 Feb 2025 15:19:34 +0000 Message-ID: <20250205151950.25268-11-alucerop@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250205151950.25268-1-alucerop@amd.com> References: <20250205151950.25268-1-alucerop@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB05.amd.com: alucerop@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017098:EE_|SN7PR12MB8789:EE_ X-MS-Office365-Filtering-Correlation-Id: 2fc7fb82-c19b-4e88-82b5-08dd45f8963c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: 8wUyzjBVphDuYS9Mla7oiH5bKn0aq600oGqObttuimvoTK5upSEGuVGyzJ6Uak3kjPSP2rbYqMM2aNrrC4wPJiCDe8AQaN8EvI/ycnC+tWcsHWAgLX2GLJWTk6XuiW5OUv86AIZftboBKsmQ/wdX4kApRafmYwG4cCNVpqILdr3H9kmjsmVbuY+yWInkkMc68ElZTH5C9OKgac+PJV0lLYYWOn9yZe2lURo9IQsPq/qUyS1dbxl43C84g1CIEFooREl6jAlhNDcMwUTOQ4m+eq4JOp3ZGYtVm1P8b2ikk3sSXuFXTHRtsYr0IlOxkAEGZ2H2jcCMebl/pazS5J6i/2YJx7tIF0uB4fayzWSHu3loGOYNp5D78spkRKlIewQr7NJFAnNNlN2l6wnuUuwh/RMsy9/0RYNRRzxQSO+7bPSn5qLgQ7udQnOG5mYEr/2H0B3HN42tXNreQ0yY3FxjSfdY/SvpNKf79o+HqAjsRpG33pWbsByxeEkZRvPzPg2Qy+2pELUvqbeSCDBmiGDpU9kwYQEXE18og26/pEqsi2qamfNGZDIOXBhvJMdpKG+xfk6J8nBwbM4ElzAprBXCnB8wrfg5kAy8rDZVlRifnHuDYA/ZhIyk9CNmzjHxH8w5l4owPz4t6JpRrnDlkFPhUK28+hGGuG3oJToC9U13i8GivLTSa0CVGnK7VWTnOLRddab30XZEIf49Z7Pp7o+a2amdEZkGNFM6Fd35I8v3P8+Iz9kdt8TCNmAf+juUiqPyXWduAM8SpJ91WZeNQLpnAIQSnl9bqTjG8Li7ebvsM0geAbqDjFBbWrgohPJcqZkJhTdEEa/bSBZ+ZLgyvgdn6ZExx7dfukVjbz2aSCJIIRN0rRui2aYDpAZeptKUZdHEyQajJfbjgDslki0eDUYQ5FuO97vcmD0xRjvsUEB0/fcBZwugb1Je8dwxZ/KOnADFEPCk7XVNv8EkMdzWkd2XMf1A+6g99k2aD6Ia8P+18Xr6JmQpPBizCWvJ8YVEwbpIX4Nyoa81lm3sCIXdyMyoG4UeWfTkA3M2omoAI0S86v+o7DSh5b1YIrGQVShMkjqeIrzzPFm+Vq9XtGZuu5YqyYwiYECIdpEZIgMr8Zwef0rg9/vmM5YhJXOg0X4bqbPP8kvN0f2UYhJhpPzp4o3+rkcUfLSaWF5FhdEKYJwpTMfyis2a+jnKK7d7LdrT4YzdSsT6dDbQNiatn9jhvWRGzQDc+ZFR/USFLN0oFWADWlvzfeCpeRRuzTLULyxLY9cKzwbroQkx/Fm4dXc+a7YO1xaTnhU5Lz1yAbB6aRYZWbJSLWgBDouQnq5R5KQoWqcYEX4RvFIakqps1X0+S9AKs68Ax6hMDjTDRz5rsNtnXtqj14BtJLvWsxtMuUilf4FmsVoeU0H6K+05fFjkgs3KP/BbJtVS6ivZmVFwhDDFsALYCaYJrnzlzKgoCV4RmpwE+2Kssj6bLh3qLlALn4qA64e5ZUf4+X/QTHth8hlx+GI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Feb 2025 15:20:13.0138 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2fc7fb82-c19b-4e88-82b5-08dd45f8963c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017098.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8789 From: Alejandro Lucero Accel drivers allocate a memdev state struct but only able to use it through the accel driver API for initialization and setup. Modify current dpa setup by drivers for realying on memdev state instead of dev state. Allow accel drivers to use dpa structs and functions. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/hdm.c | 4 +++- drivers/cxl/cxl.h | 6 +----- drivers/cxl/cxlmem.h | 14 -------------- drivers/cxl/pci.c | 2 +- include/cxl/cxl.h | 19 +++++++++++++++++++ 5 files changed, 24 insertions(+), 21 deletions(-) diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c index d705dec1471e..af025da81fa2 100644 --- a/drivers/cxl/core/hdm.c +++ b/drivers/cxl/core/hdm.c @@ -467,8 +467,10 @@ static const char *cxl_mode_name(enum cxl_partition_mode mode) } /* if this fails the caller must destroy @cxlds, there is no recovery */ -int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info) +int cxl_dpa_setup(struct cxl_memdev_state *cxlmds, + const struct cxl_dpa_info *info) { + struct cxl_dev_state *cxlds = &cxlmds->cxlds; struct device *dev = cxlds->dev; guard(rwsem_write)(&cxl_dpa_rwsem); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 27d1dc48611c..3faba6c9dbfb 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -11,6 +11,7 @@ #include #include #include +#include extern const struct nvdimm_security_ops *cxl_security_ops; @@ -478,11 +479,6 @@ struct cxl_region_params { int nr_targets; }; -enum cxl_partition_mode { - CXL_PARTMODE_RAM, - CXL_PARTMODE_PMEM, -}; - /* * Indicate whether this region has been assembled by autodetection or * userspace assembly. Prevent endpoint decoders outside of automatic diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index ab8c23009b9d..a5994061780c 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -98,19 +98,6 @@ int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, resource_size_t base, resource_size_t len, resource_size_t skipped); -#define CXL_NR_PARTITIONS_MAX 2 - -struct cxl_dpa_info { - u64 size; - struct cxl_dpa_part_info { - struct range range; - enum cxl_partition_mode mode; - } part[CXL_NR_PARTITIONS_MAX]; - int nr_partitions; -}; - -int cxl_dpa_setup(struct cxl_dev_state *cxlds, const struct cxl_dpa_info *info); - static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port, struct cxl_memdev *cxlmd) { @@ -841,7 +828,6 @@ int cxl_internal_send_cmd(struct cxl_mailbox *cxl_mbox, struct cxl_mbox_cmd *cmd); int cxl_dev_state_identify(struct cxl_memdev_state *mds); int cxl_enumerate_cmds(struct cxl_memdev_state *mds); -int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info); struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial, u16 dvsec, enum cxl_devtype type); void set_exclusive_cxl_commands(struct cxl_memdev_state *mds, diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 5fe5f7ff4fb1..bcfa3d86c37b 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -955,7 +955,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) return rc; - rc = cxl_dpa_setup(cxlds, &range_info); + rc = cxl_dpa_setup(mds, &range_info); if (rc) return rc; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 1b2224ee1d5b..ec56a82966c0 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -49,6 +49,23 @@ struct mds_info { u64 persistent_only_bytes; }; +enum cxl_partition_mode { + CXL_PARTMODE_NONE, + CXL_PARTMODE_RAM, + CXL_PARTMODE_PMEM, +}; + +#define CXL_NR_PARTITIONS_MAX 2 + +struct cxl_dpa_info { + u64 size; + struct cxl_dpa_part_info { + struct range range; + enum cxl_partition_mode mode; + } part[CXL_NR_PARTITIONS_MAX]; + int nr_partitions; +}; + struct device; struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev, u64 serial, u16 dvsec, enum cxl_devtype type); @@ -59,4 +76,6 @@ int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_memdev_state *cxlm int cxl_await_media_ready(struct cxl_memdev_state *mds); void cxl_set_media_ready(struct cxl_memdev_state *mds); void cxl_dev_state_setup(struct cxl_memdev_state *mds, struct mds_info *info); +int cxl_mem_dpa_fetch(struct cxl_memdev_state *mds, struct cxl_dpa_info *info); +int cxl_dpa_setup(struct cxl_memdev_state *cxlmds, const struct cxl_dpa_info *info); #endif