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Wed, 5 Feb 2025 09:20:01 -0600 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v10 03/26] cxl: move pci generic code Date: Wed, 5 Feb 2025 15:19:27 +0000 Message-ID: <20250205151950.25268-4-alucerop@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250205151950.25268-1-alucerop@amd.com> References: <20250205151950.25268-1-alucerop@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017099:EE_|DM4PR12MB6301:EE_ X-MS-Office365-Filtering-Correlation-Id: d14b1d66-8dd5-4f69-a9c1-08dd45f89082 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: KwkpojzqrgSut4avc1AU5mIz0rVkzfz8ZvSXn+fu9bpYi2wuFgC/1C3golHnotNciQI0XP+zsjWrJ02fjhw/90mr7fI5BsfnvGR9yWrVFpDPaf3/WufZ3Tc+9mKMf5jrUwZkfcszXBf9hTvWWS5j8sstlBj7b5R5aqpwjQslr+OwORA2LYQxVQK8BybtjY2Yh4P1IWf1EnQBsOuhiZPHF+GGTE5JaTe5myYuaig3q3eATeKAhbIFM0474yl2rCKRFQbN5D+S/acYYsoE3CTKJdDCdj85dJmCeJJlXqHJUs8tjX0tjI/v5NuaQkQA5rBgFqLRMCYgJSskevcTMH3AqA4yDqPwt9zH/DbVsGYL5kHaFuX8C9xxfQNUEqYejDvQwwdY+VNRznUGMPcZss4jPWd5FicNEdEFfnWF1NhWmEJCd/Tpr02y3cxlpcllAHQftInIcrcfTIYwFgCK+IbRpDiDjF+tr3kn/SptJ4GLiBQT7uss7lL+HNrEfegQaj+vE/rQOzd7fjsakkbSI4mJ2QnfEDMDMpqEy9DN6rdHR1KS8aBrNTOiloz4u0gD2QihKHNPGaJMgbz7ocleLTPNbbcBO8QhEXMgwVkD/REzy8EmPfzNtQgx78nm/hY/CMghuC1zGmDFtLQiHZqX6QEx+a33IyT05bZr14W4IwmDsN/0rvoG8WkCPY6QQkkTDE/X7fQNX0yhYwYOgNSo8ZvD3gV59Y/WU6DsbS353/Siy7xgI0iJGwLVWLQBQVOUNxsOFt5KIZD+pApgMZHusAhJerlATQd3LS0MlclPcg+CoBYLyal0fDdvq+No/4OS+5KoX7OFWOP74K1GGrs4cAJhjgjAfg5dLnLAqDGGMbCNdnpKb5dhAmGL8pUgbgbU0cr3I5RNWp1+Lver0LqHNTw+43iaYKxtSIPT/wqaQPukjETggCPp46ySQ9RA15MAmSpgW5xCWdXZUzjKnnFkOkPCTXefk/kO9fJ39BNWhHVz2XP0UBABxbLlv7cyP3w1ZU67udTWYPamIJsaLSQc3OYhHbaCFCTr3NTyQqr/+ORsqrkz6v6MQZl3XebaKtrew+47pWNp+/lNYquPssRTVFcWoZbED70gKWQ8PlgMt2trFXxRB1hGO7GDBF50PIPBec6rs7y7t3xJAhnH8LIHEazHbTUhn74FcTkoEAudcd8YJMar6+ks7uTOFgBYu3WV7JeuxfDFRS6NpR64roe62O+oVwP1N87uiT6uJDZ4cFY9BSxPvOThP3R/K1V7feem7c6sbSI5C8Y6NwySqEN5QKnNpSwyZpkSj62uqCuy8KMJa3n8zCYRLDPxj45YCMPmKrfuxcmMESMathfKV66Sx44P0F015fJWbtjeCTviE1PwdgVK5alqdSdqspLxGziGersdOIpC9yKN8at0V/HFzKg8HR0sdQ9Ci0ykcHar2jTHjpfO3p+K/vs5u6dtLcKytm2VtIax7fzy15vldpmT09+Lb/6rC6caJIHQL63kHhJ51WU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Feb 2025 15:20:03.4072 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d14b1d66-8dd5-4f69-a9c1-08dd45f89082 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017099.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6301 From: Alejandro Lucero Inside cxl/core/pci.c there are helpers for CXL PCIe initialization meanwhile cxl/pci.c implements the functionality for a Type3 device initialization. Move helper functions from cxl/pci.c to cxl/core/pci.c in order to be exported and shared with CXL Type2 device initialization. Signed-off-by: Alejandro Lucero Reviewed-by: Dave Jiang Reviewed-by: Ben Cheatham Reviewed-by: Fan Ni Reviewed-by: Jonathan Cameron --- drivers/cxl/core/core.h | 2 + drivers/cxl/core/pci.c | 62 +++++++++++++++++++++++++++++++ drivers/cxl/core/regs.c | 1 - drivers/cxl/cxl.h | 2 - drivers/cxl/cxlpci.h | 2 + drivers/cxl/pci.c | 70 ----------------------------------- include/cxl/pci.h | 17 ++++++++- tools/testing/cxl/Kbuild | 1 - tools/testing/cxl/test/mock.c | 17 --------- 9 files changed, 81 insertions(+), 93 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 02971e0115c5..9bcc7aa7d434 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -107,6 +107,8 @@ enum cxl_poison_trace_type { CXL_POISON_TRACE_CLEAR, }; +resource_size_t cxl_rcd_component_reg_phys(struct device *dev, + struct cxl_dport *dport); long cxl_pci_get_latency(struct pci_dev *pdev); int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c); int cxl_update_hmat_access_coordinates(int nid, struct cxl_region *cxlr, diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index a5c65f79db18..f153ccd87dab 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1032,6 +1032,68 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, "CXL"); +static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, + struct cxl_register_map *map, + struct cxl_dport *dport) +{ + resource_size_t component_reg_phys; + + *map = (struct cxl_register_map) { + .host = &pdev->dev, + .resource = CXL_RESOURCE_NONE, + }; + + struct cxl_port *port __free(put_cxl_port) = + cxl_pci_find_port(pdev, &dport); + if (!port) + return -EPROBE_DEFER; + + component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); + if (component_reg_phys == CXL_RESOURCE_NONE) + return -ENXIO; + + map->resource = component_reg_phys; + map->reg_type = CXL_REGLOC_RBI_COMPONENT; + map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; + + return 0; +} + +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map) +{ + int rc; + + rc = cxl_find_regblock(pdev, type, map); + + /* + * If the Register Locator DVSEC does not exist, check if it + * is an RCH and try to extract the Component Registers from + * an RCRB. + */ + if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) { + struct cxl_dport *dport; + struct cxl_port *port __free(put_cxl_port) = + cxl_pci_find_port(pdev, &dport); + if (!port) + return -EPROBE_DEFER; + + rc = cxl_rcrb_get_comp_regs(pdev, map, dport); + if (rc) + return rc; + + rc = cxl_dport_map_rcd_linkcap(pdev, dport); + if (rc) + return rc; + + } else if (rc) { + return rc; + } + + return cxl_setup_regs(map); +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, "CXL"); + int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) { int speed, bw; diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 117c2e94c761..7d025d38da07 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -645,4 +645,3 @@ resource_size_t cxl_rcd_component_reg_phys(struct device *dev, return CXL_RESOURCE_NONE; return __rcrb_to_component(dev, &dport->rcrb, CXL_RCRB_UPSTREAM); } -EXPORT_SYMBOL_NS_GPL(cxl_rcd_component_reg_phys, "CXL"); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 6baec4ba9141..74bccf55c8dc 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -311,8 +311,6 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, struct cxl_register_map *map); int cxl_setup_regs(struct cxl_register_map *map); struct cxl_dport; -resource_size_t cxl_rcd_component_reg_phys(struct device *dev, - struct cxl_dport *dport); int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); #define CXL_RESOURCE_NONE ((resource_size_t) -1) diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 9fcf5387e388..735668f8cca6 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -120,4 +120,6 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index bd69dc07f387..39df0ff3af50 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -465,76 +465,6 @@ static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds, bool irq_avail) return 0; } -/* - * Assume that any RCIEP that emits the CXL memory expander class code - * is an RCD - */ -static bool is_cxl_restricted(struct pci_dev *pdev) -{ - return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; -} - -static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, - struct cxl_register_map *map, - struct cxl_dport *dport) -{ - resource_size_t component_reg_phys; - - *map = (struct cxl_register_map) { - .host = &pdev->dev, - .resource = CXL_RESOURCE_NONE, - }; - - struct cxl_port *port __free(put_cxl_port) = - cxl_pci_find_port(pdev, &dport); - if (!port) - return -EPROBE_DEFER; - - component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); - if (component_reg_phys == CXL_RESOURCE_NONE) - return -ENXIO; - - map->resource = component_reg_phys; - map->reg_type = CXL_REGLOC_RBI_COMPONENT; - map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; - - return 0; -} - -static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, - struct cxl_register_map *map) -{ - int rc; - - rc = cxl_find_regblock(pdev, type, map); - - /* - * If the Register Locator DVSEC does not exist, check if it - * is an RCH and try to extract the Component Registers from - * an RCRB. - */ - if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) { - struct cxl_dport *dport; - struct cxl_port *port __free(put_cxl_port) = - cxl_pci_find_port(pdev, &dport); - if (!port) - return -EPROBE_DEFER; - - rc = cxl_rcrb_get_comp_regs(pdev, map, dport); - if (rc) - return rc; - - rc = cxl_dport_map_rcd_linkcap(pdev, dport); - if (rc) - return rc; - - } else if (rc) { - return rc; - } - - return cxl_setup_regs(map); -} - static int cxl_pci_ras_unmask(struct pci_dev *pdev) { struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); diff --git a/include/cxl/pci.h b/include/cxl/pci.h index ad63560caa2c..e6178aa341b2 100644 --- a/include/cxl/pci.h +++ b/include/cxl/pci.h @@ -1,8 +1,21 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ -#ifndef __CXL_ACCEL_PCI_H -#define __CXL_ACCEL_PCI_H +#ifndef __LINUX_CXL_PCI_H +#define __LINUX_CXL_PCI_H + +#include + +/* + * Assume that the caller has already validated that @pdev has CXL + * capabilities, any RCIEp with CXL capabilities is treated as a + * Restricted CXL Device (RCD) and finds upstream port and endpoint + * registers in a Root Complex Register Block (RCRB). + */ +static inline bool is_cxl_restricted(struct pci_dev *pdev) +{ + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; +} /* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */ #define CXL_DVSEC_PCIE_DEVICE 0 diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index b1256fee3567..e20d0e767574 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -12,7 +12,6 @@ ldflags-y += --wrap=cxl_await_media_ready ldflags-y += --wrap=cxl_hdm_decode_init ldflags-y += --wrap=cxl_dvsec_rr_decode ldflags-y += --wrap=devm_cxl_add_rch_dport -ldflags-y += --wrap=cxl_rcd_component_reg_phys ldflags-y += --wrap=cxl_endpoint_parse_cdat ldflags-y += --wrap=cxl_dport_init_ras_reporting diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index af2594e4f35d..3c6a071fbbe3 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -268,23 +268,6 @@ struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct cxl_port *port, } EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, "CXL"); -resource_size_t __wrap_cxl_rcd_component_reg_phys(struct device *dev, - struct cxl_dport *dport) -{ - int index; - resource_size_t component_reg_phys; - struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); - - if (ops && ops->is_mock_port(dev)) - component_reg_phys = CXL_RESOURCE_NONE; - else - component_reg_phys = cxl_rcd_component_reg_phys(dev, dport); - put_cxl_mock_ops(index); - - return component_reg_phys; -} -EXPORT_SYMBOL_NS_GPL(__wrap_cxl_rcd_component_reg_phys, "CXL"); - void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port) { int index;