| Message ID | 20250220-gianfar-yaml-v1-2-0ba97fd1ef92@posteo.net (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: Convert Gianfar (Triple Speed Ethernet Controller) bindings to YAML | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Not a local patch |
On Thu, 20 Feb 2025 18:29:22 +0100, J. Neuschäfer wrote: > When this binding was originally written, all known TSEC Ethernet > controllers had a Ten-Bit Interface (TBI). However, some datasheets such > as for the MPC8315E suggest that this is not universally true: > > The eTSECs do not support TBI, GMII, and FIFO operating modes, so all > references to these interfaces and features should be ignored for this > device. > > Signed-off-by: J. Neuschäfer <j.ne@posteo.net> > --- > Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml | 13 ++++++------- > 1 file changed, 6 insertions(+), 7 deletions(-) > Acked-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml b/Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml index 2dade7f48c366b7f5c7408e1f7de1a6f5fc80787..0d2605512c4711a4dcb77620b94ea77a71b45fa8 100644 --- a/Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml +++ b/Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml @@ -11,13 +11,12 @@ description: connected. For each device that exists on this bus, a child node should be created. - As of this writing, every TSEC is associated with an internal Ten-Bit - Interface (TBI) PHY. This PHY is accessed through the local MDIO bus. These - buses are defined similarly to the mdio buses, except they are compatible - with "fsl,gianfar-tbi". The TBI PHYs underneath them are similar to normal - PHYs, but the reg property is considered instructive, rather than - descriptive. The reg property should be chosen so it doesn't interfere with - other PHYs on the bus. + Some TSECs are associated with an internal Ten-Bit Interface (TBI) PHY. This + PHY is accessed through the local MDIO bus. These buses are defined similarly + to the mdio buses, except they are compatible with "fsl,gianfar-tbi". The TBI + PHYs underneath them are similar to normal PHYs, but the reg property is + considered instructive, rather than descriptive. The reg property should be + chosen so it doesn't interfere with other PHYs on the bus. maintainers: - J. Neuschäfer <j.ne@posteo.net>