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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: Gal Pressman , Mark Bloch , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , , , , Jianbo Liu , "Leon Romanovsky" , Patrisious Haddad Subject: [PATCH net-next 2/8] net/mlx5e: Change the destination of IPSec RX SA miss rule Date: Thu, 20 Feb 2025 23:39:52 +0200 Message-ID: <20250220213959.504304-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.45.0 In-Reply-To: <20250220213959.504304-1-tariqt@nvidia.com> References: <20250220213959.504304-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C9:EE_|DM4PR12MB5844:EE_ X-MS-Office365-Filtering-Correlation-Id: 52af04de-1197-41cc-b8ec-08dd51f74b1d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: JLMrh5B+Tir6U5llH13kM1D7KMe4JkkTNw4f4aOfNaYiu53UyQjOZh25s0z9K8AFxjNhI5PSzn5FsU5ueTpT/xb0tHBuPo+6AeNWi/Q6H+4UUZfNLY7NSVC4wv6RfNq+8clvV2g2hbAppCryCOpnI0iDqwN2Aomoh0QfaTTRNwdZN6qhslpr/UuZzuvqOl/SWyo9fM4rwU3ENjAGCHJKIJFeZDCeScuMeykLImQQbMabCv0819ZZwHBloEz2EI5JIqOzfp45a6XprvisjY8W3sIryxsaBSRgQcRHsCGQGrdcimrtO/zUBtlx1+EqnKDRoPrDOufBRtEaYa3iUf11GwnFU/0wBP4B9FQ7umBPshRSmHJj1rWUqjsvbPRJaJzz3FfirMAnUy1xMmrnJHCt7TIVtMmxF8/+r6PiYtEkTWXjHrDXeV647zD+Pe7l9wnY3s6ceTxJCy9VcMf9Shs3tF0XPCYHLIaQQ3rAJunpNV85ctC+nWl4ahCSfeoE+HNBWTC8GTW+NyvmmwKq9ZIm9ApSjZj7HWM8SIFg4a3E1RyQ7vmW2ZLWe7cEBYzFe/WKSHfIGHo+N5w6IYqFXpgQiEC57evwBR8K85XiGZSL/+yGKa1Os6GMFJjyPrcko0SyjLMXXcLhBijCVYomUcOxFmUwd8nIilvghjZeTHvueNGN1lJKiuM+weP3CgcjrjV4m9wLkPjVFyAnkbDm9zaET+4CrfrwS9gYe87gzYOJlIKSi5te4LqHeV/qXlQlxfmH6Zh84+pTKwt35id5ATZX/dssACmd5qmWo5UEasOxfB1Q9IzJxTKffOzCWOVV34E/RgePJGL2CjONqTCT2yLSiTuj1wTK5RaYhcT7T89quWxzmjkpt/2h3+NTM1hUhn6obX0P2H5Y+wDFOJOkXjwVKer1qh6XbzShlGA5P5FagiSquPPaWELMqbpvX5JN42ZgKODKCuFrNWVvPiRFvPeHS+D/Xr+meVFjweXu/NOFR6y/gGlLRoFMPbhYwkTrNv1RCjq1yONG12fbGWqRC/kb4E17UPpkEKvyCi38ZvPqU+ReQvccYKFKd7xssm4o5pdIrWYeAZD5wLbEpzSlFjMKJR4vFaO31jB/AkD68mpbFsvTeLu3MnscjD2DySWbTZMUhRXaInkzDMNGjA4Mt/K0uvomoNydY+wl9b0nz7NimP7pPdtd2Ko53btzFDBmNBCd/bPnYz96obZowwAxWKODYdTXRzbf1nu5oMbdQxqQYJCP/zn4YWcGskbbEH1o1N6jPq0zfl9IiFhdqi019kq+/c0UwXR0uncEq5ULkjqlHA6v//rgRlrYvNrVkfQCuhEZEvpOoOSLY2LTg1xgu3/24wmLPyG1hzN0mY0R9cjQFnmqtrYdE0/kfXfuJBJlZiS6FPpBfzEOPvaYARgcCWvRGpuhkgNUOgJ+JuEyAGkudvE8BFSEMRyTAiI5rPEn6Iio64kAKvnd0irVDnfhYe3pPede/9VPzPn3k8TH6t8tLek= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Feb 2025 21:41:11.4395 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52af04de-1197-41cc-b8ec-08dd51f74b1d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C9.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5844 X-Patchwork-Delegate: kuba@kernel.org From: Jianbo Liu For eswitch in legacy mode, the packets decrypted in RX SA table will continue to be processed for RoCE. But this is not necessary for the un-decrypted packets, which don't match any decryption rules but hit the miss rule at the end of the table. So, change the destination of miss rule to TTC default one and skip RoCE. For eswitch in switchdev mode, the destination is unchanged. Signed-off-by: Jianbo Liu Reviewed-by: Leon Romanovsky Reviewed-by: Patrisious Haddad Signed-off-by: Tariq Toukan --- .../mellanox/mlx5/core/en_accel/ipsec_fs.c | 20 ++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c index 7f82d530d3e1..7c9fdea21366 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_fs.c @@ -498,7 +498,6 @@ static void ipsec_rx_update_default_dest(struct mlx5e_ipsec_rx *rx, struct mlx5_flow_destination *new_dest) { mlx5_modify_rule_destination(rx->status.rule, new_dest, old_dest); - mlx5_modify_rule_destination(rx->sa.rule, new_dest, old_dest); } static void handle_ipsec_rx_bringup(struct mlx5e_ipsec *ipsec, u32 family) @@ -658,6 +657,20 @@ static int ipsec_rx_status_pass_dest_get(struct mlx5e_ipsec *ipsec, return 0; } +static void ipsec_rx_sa_miss_dest_get(struct mlx5e_ipsec *ipsec, + struct mlx5e_ipsec_rx *rx, + struct mlx5e_ipsec_rx_create_attr *attr, + struct mlx5_flow_destination *dest, + struct mlx5_flow_destination *miss_dest) +{ + if (rx == ipsec->rx_esw) + *miss_dest = *dest; + else + *miss_dest = + mlx5_ttc_get_default_dest(attr->ttc, + family2tt(attr->family)); +} + static void ipsec_rx_ft_connect(struct mlx5e_ipsec *ipsec, struct mlx5e_ipsec_rx *rx, struct mlx5e_ipsec_rx_create_attr *attr) @@ -672,8 +685,8 @@ static void ipsec_rx_ft_connect(struct mlx5e_ipsec *ipsec, static int rx_create(struct mlx5_core_dev *mdev, struct mlx5e_ipsec *ipsec, struct mlx5e_ipsec_rx *rx, u32 family) { + struct mlx5_flow_destination dest[2], miss_dest; struct mlx5e_ipsec_rx_create_attr attr; - struct mlx5_flow_destination dest[2]; struct mlx5_flow_table *ft; u32 flags = 0; int err; @@ -709,7 +722,8 @@ static int rx_create(struct mlx5_core_dev *mdev, struct mlx5e_ipsec *ipsec, } rx->ft.sa = ft; - err = ipsec_miss_create(mdev, rx->ft.sa, &rx->sa, dest); + ipsec_rx_sa_miss_dest_get(ipsec, rx, &attr, &dest[0], &miss_dest); + err = ipsec_miss_create(mdev, rx->ft.sa, &rx->sa, &miss_dest); if (err) goto err_fs;