From patchwork Fri Feb 21 12:31:21 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Grzegorz Nitka X-Patchwork-Id: 13985390 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3976F20B1E4 for ; Fri, 21 Feb 2025 12:35:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740141305; cv=none; b=Elrp66zMwmVhAzaF4ar9qxqB++ObsUno6u3whNu/n0t91AVaxCi5ZzLwBtYtpPT/ACogHvt7rl28M05NchFPBEh9CIf3oPV37KzO17W3o3Usn9wn3x6oRGjoSEXkleN2yctezJyiCclddYN1cRlRN+1fz1tgklIglExMk25b6bM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740141305; c=relaxed/simple; bh=OokhZU0ucJA3wv81A0URemxNst8DeX54Kzy94AdQM0Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=G/lswc34gHRBfADoSimSrB68ybFGvWmX6r7V5PO9V60j/mD84iIQGCwkCFl9VG8r+kYXObTNItlPTLQ9X3XH45x5HVXWh/iR/dk1RxR5NFH4JbLFgiOI0dot3GuR5s13CjMGvGncgHtnd3uJ8/Cc+GgK5SG6DMFXpD4g2BRuWCA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=BbUJORKd; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="BbUJORKd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740141304; x=1771677304; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OokhZU0ucJA3wv81A0URemxNst8DeX54Kzy94AdQM0Y=; b=BbUJORKdmaTdsrBxWjuT8U1KzwdtA23i8AvctX2Vj4vJCtUSKM0+OLJR 9MpKbLulVm8TGclvvMYmaUWmdwThy9VYH3P/exYdmLU4EO99Pf0J+PxF3 a4VkAhJF+8pb0WkZDhiHBExEFBuI6Uq9HGKNhg4CVtp8emXRVZA72s5rd FCUPZ9Zglbi+gKh9SsN3JXxITmyB+f/ec9+cHnfQhwdMmlQKgEwNEolH1 q3QyA5i5Q05RZNrsHml3Cc7PdX2IHe669xAqk3Ua7C7G8+RhEs/5/GXTr /lDtuLIXY887ddkIf8Y6TVdVP5EpwDuuh/tIjX9rcSpbOIrxjOez6ckwh w==; X-CSE-ConnectionGUID: YrUwJ9hEShSlHUQYEhtv/g== X-CSE-MsgGUID: AyKCRNivR1ibIuuLuXIitA== X-IronPort-AV: E=McAfee;i="6700,10204,11351"; a="66321394" X-IronPort-AV: E=Sophos;i="6.13,304,1732608000"; d="scan'208";a="66321394" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Feb 2025 04:35:04 -0800 X-CSE-ConnectionGUID: WRG5IlcUR5ea/qOPxAw4jw== X-CSE-MsgGUID: p5nbd5RwQ4qRTvaUJ+i0PA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="115862562" Received: from gklab-003-001.igk.intel.com ([10.211.3.1]) by orviesa007.jf.intel.com with ESMTP; 21 Feb 2025 04:35:03 -0800 From: Grzegorz Nitka To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, Karol Kolacinski , Michal Swiatkowski , Przemek Kitszel , Grzegorz Nitka Subject: [PATCH iwl-next v1 1/3] ice: remove SW side band access workaround for E825 Date: Fri, 21 Feb 2025 13:31:21 +0100 Message-Id: <20250221123123.2833395-2-grzegorz.nitka@intel.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250221123123.2833395-1-grzegorz.nitka@intel.com> References: <20250221123123.2833395-1-grzegorz.nitka@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Karol Kolacinski Due to the bug in FW/NVM autoload mechanism (wrong default SB_REM_DEV_CTL register settings), the access to peer PHY and CGU clients was disabled by default. As the workaround solution, the register value was overwritten by the driver at the probe or reset handling. Remove workaround as it's not needed anymore. The fix in autoload procedure has been provided with NVM 3.80 version. Reviewed-by: Michal Swiatkowski Reviewed-by: Przemek Kitszel Signed-off-by: Karol Kolacinski Signed-off-by: Grzegorz Nitka --- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 23 --------------------- 1 file changed, 23 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 89bb8461284a..a5df081ffc19 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -2630,25 +2630,6 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) return 0; } -/** - * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access - * @hw: pointer to HW struct - * @enable: Enable or disable access - * - * Enable sideband devices (PHY and others) access. - */ -static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) -{ - u32 val = rd32(hw, PF_SB_REM_DEV_CTL); - - if (enable) - val |= BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1); - else - val &= ~(BIT(eth56g_phy_0) | BIT(cgu) | BIT(eth56g_phy_1)); - - wr32(hw, PF_SB_REM_DEV_CTL, val); -} - /** * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization * @hw: pointer to HW struct @@ -2659,8 +2640,6 @@ static void ice_sb_access_ena_eth56g(struct ice_hw *hw, bool enable) */ static int ice_ptp_init_phc_e825(struct ice_hw *hw) { - ice_sb_access_ena_eth56g(hw, true); - /* Initialize the Clock Generation Unit */ return ice_init_cgu_e82x(hw); } @@ -2747,8 +2726,6 @@ static void ice_ptp_init_phy_e825(struct ice_hw *hw) params->num_phys = 2; ptp->ports_per_phy = 4; ptp->num_lports = params->num_phys * ptp->ports_per_phy; - - ice_sb_access_ena_eth56g(hw, true); } /* E822 family functions