| Message ID | 20250303102739.137058-1-viktar.palstsiuk@dewesoft.com (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: phy: dp83869: fix status reporting for speed optimization | expand |
On Mon, Mar 03, 2025 at 11:27:39AM +0100, Viktar Palstsiuk wrote: > Speed optimization is enabled for the PHY, but unlike the DP83867, > the DP83869 driver does not take the PHY status register into account. Is speed optimisation another name for downshift? When the cable is broken, the PHY will find two pairs that work and use 100Mbps over them? In the kernel we call this downshift. Andrew
Yes, the term "speed optimization" is used in the DP83869 datasheet for downshift. Viktar On Mon, Mar 3, 2025 at 2:31 PM Andrew Lunn <andrew@lunn.ch> wrote: > > On Mon, Mar 03, 2025 at 11:27:39AM +0100, Viktar Palstsiuk wrote: > > Speed optimization is enabled for the PHY, but unlike the DP83867, > > the DP83869 driver does not take the PHY status register into account. > > Is speed optimisation another name for downshift? When the cable is > broken, the PHY will find two pairs that work and use 100Mbps over > them? In the kernel we call this downshift. > > Andrew
On Mon, Mar 03, 2025 at 04:41:54PM +0100, Viktar Palstsiuk wrote: > Yes, the term "speed optimization" is used in the DP83869 datasheet > for downshift. Please could you reword the commit message to use both the datasheet terminology and the kernel terminology. That makes the change easier to understand for everybody. Andrew --- pw-bot: cr
diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c index a62cd838a9ea..fd61d4fbe81d 100644 --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c @@ -20,6 +20,7 @@ #define DP83869_DEVADDR 0x1f #define MII_DP83869_PHYCTRL 0x10 +#define MII_DP83869_PHYSTS 0x11 #define MII_DP83869_MICR 0x12 #define MII_DP83869_ISR 0x13 #define DP83869_CFG2 0x14 @@ -123,6 +124,12 @@ #define DP83869_WOL_SEC_EN BIT(5) #define DP83869_WOL_ENH_MAC BIT(7) +/* PHY STS bits */ +#define DP83869_PHYSTS_1000 BIT(15) +#define DP83869_PHYSTS_100 BIT(14) +#define DP83869_PHYSTS_DUPLEX BIT(13) +#define DP83869_PHYSTS_LINK BIT(10) + /* CFG2 bits */ #define DP83869_DOWNSHIFT_EN (BIT(8) | BIT(9)) #define DP83869_DOWNSHIFT_ATTEMPT_MASK (BIT(10) | BIT(11)) @@ -165,6 +172,7 @@ static int dp83869_config_aneg(struct phy_device *phydev) static int dp83869_read_status(struct phy_device *phydev) { + int status = phy_read(phydev, MII_DP83869_PHYSTS); struct dp83869_private *dp83869 = phydev->priv; bool changed; int ret; @@ -185,6 +193,21 @@ static int dp83869_read_status(struct phy_device *phydev) } } + if (status < 0) + return status; + + if (status & DP83869_PHYSTS_DUPLEX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + if (status & DP83869_PHYSTS_1000) + phydev->speed = SPEED_1000; + else if (status & DP83869_PHYSTS_100) + phydev->speed = SPEED_100; + else + phydev->speed = SPEED_10; + return 0; }
Speed optimization is enabled for the PHY, but unlike the DP83867, the DP83869 driver does not take the PHY status register into account. Update link speed and duplex settings based on the DP83869 PHY status register, which is necessary when speed optimization occurs. Signed-off-by: Viktar Palstsiuk <viktar.palstsiuk@dewesoft.com> --- drivers/net/phy/dp83869.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)