From patchwork Fri Mar 28 13:35:43 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 14031992 Received: from mx.denx.de (mx.denx.de [89.58.32.78]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1EBA21D5BD; Fri, 28 Mar 2025 13:36:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=89.58.32.78 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743168979; cv=none; b=MOANn6rfhTEfhq6mNfwb/hQO9t49DYZX68ahNuRpFkAsVH6XJJ8P3rzlUtTo3On3To267QATOQhF0YZdgeIFxQCSj5J2XVr4IjgEEz3o7QnF+OdxMUVys6sBRMkgkXTr+gKqbXe352JTdxy4zxQMRBouAozqwiaz8EIk3e7MuOM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743168979; c=relaxed/simple; bh=yEpggcpuVid2q++y2sd8rlBoSpPaih4tW7/nEPlCUPk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZIASV0PH9jishW9tFIMpwfNlgXLxvD1fS4VED3+RmMeScq6kI1UEgf8LNu0/vJu+nomRWHETNrwSImHXUlhboCNsS34+QO0G9VwsmS/0CNDxsrj4NPn+dTQkLVEDBWJ21vk02P1wPPUjeUN+ihlJfvaPc9PcVp7az7XnAZivXY4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de; spf=pass smtp.mailfrom=denx.de; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b=dmOsNQum; arc=none smtp.client-ip=89.58.32.78 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=denx.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=denx.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=denx.de header.i=@denx.de header.b="dmOsNQum" Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 6C2F1101DC317; Fri, 28 Mar 2025 14:36:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=mx-20241105; t=1743168975; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=L80ILDklNc/jTkYuHdpUJa7vnQWj69oUTO5Sxx/K1eM=; b=dmOsNQumOPA+x++MjxWkbGPSesX7GRU+ATnVJRmRQjMFFym+dxxbQ2MCCDFIBSYgf/MXgZ CEQUo3iw3PiOrdCZnFMqqblQKBYulwEY20c/gc/k3BhMpx/fGhd5JP7G/8Nrka8Xqwbyms wzCHR/QEGwnQjWAUzG7aZzla0qnB5/Ii+Wx6yBlFEkZFt3tXpP1IDtHy1fuHB1XKbkrqU0 ox5Iuxm/xOb8uo2SGkX+Ez1kdnfrLfiQb9UYORHrLfGH1acLDUQApgtwDI88efI6ybFDM5 8hxWEUP5FlJxljSSwI0M7gOHpN861h/2JGmqEaBBpntucL2xd2+zfkIxEdqOJg== From: Lukasz Majewski To: Andrew Lunn , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo Cc: Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Richard Cochran , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Lukasz Majewski Subject: [PATCH v2 3/4] ARM: dts: nxp: mxs: Adjust XEA board's DTS to support L2 switch Date: Fri, 28 Mar 2025 14:35:43 +0100 Message-Id: <20250328133544.4149716-4-lukma@denx.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250328133544.4149716-1-lukma@denx.de> References: <20250328133544.4149716-1-lukma@denx.de> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Last-TLS-Session-Version: TLSv1.3 The description is similar to the one used with the new CPSW driver. Signed-off-by: Lukasz Majewski --- Changes for v2: - Remove properties which are common for the imx28(7) SoC - Use mdio properties to perform L2 switch reset (avoid using deprecated properties) --- arch/arm/boot/dts/nxp/mxs/imx28-xea.dts | 54 +++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts index 6c5e6856648a..d5558e24844c 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-xea.dts @@ -5,6 +5,7 @@ */ /dts-v1/; +#include #include "imx28-lwe.dtsi" / { @@ -90,6 +91,59 @@ ®_usb_5v { gpio = <&gpio0 2 0>; }; +ð_switch { + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>, <&mac1_pins_a>; + phy-supply = <®_fec_3v3>; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + mtip_port1: port@1 { + reg = <1>; + label = "lan0"; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + }; + + mtip_port2: port@2 { + reg = <2>; + label = "lan1"; + local-mac-address = [ 00 00 00 00 00 00 ]; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + }; + }; + + mdio_sw: mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio3 21 0>; + reset-delay-us = <25000>; + reset-post-delay-us = <10000>; + + ethphy0: ethernet-phy@0 { + reg = <0>; + smsc,disable-energy-detect; + /* Both PHYs (i.e. 0,1) have the same, single GPIO, */ + /* line to handle both, their interrupts (AND'ed) */ + interrupt-parent = <&gpio4>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + }; + + ethphy1: ethernet-phy@1 { + reg = <1>; + smsc,disable-energy-detect; + interrupt-parent = <&gpio4>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + }; + }; +}; + &spi2_pins_a { fsl,pinmux-ids = < MX28_PAD_SSP2_SCK__SSP2_SCK