diff mbox series

[net-next,2/6] mlxsw: reg: Add Management Capabilities Mask Register

Message ID 21a273b68773c4cbc47dbc4521cbc7dedc3391c4.1679502371.git.petrm@nvidia.com (mailing list archive)
State Changes Requested
Delegated to: Netdev Maintainers
Headers show
Series mlxsw: Add support for new reset flow | expand

Checks

Context Check Description
netdev/series_format success Posting correctly formatted
netdev/tree_selection success Clearly marked for net-next
netdev/fixes_present success Fixes tag not required for -next series
netdev/header_inline success No static functions without inline keyword in header files
netdev/build_32bit success Errors and warnings before: 18 this patch: 18
netdev/cc_maintainers success CCed 7 of 7 maintainers
netdev/build_clang success Errors and warnings before: 18 this patch: 18
netdev/verify_signedoff success Signed-off-by tag matches author and committer
netdev/deprecated_api success None detected
netdev/check_selftest success No net selftest shell script
netdev/verify_fixes success No Fixes tag
netdev/build_allmodconfig_warn success Errors and warnings before: 18 this patch: 18
netdev/checkpatch warning WARNING: Missing a blank line after declarations
netdev/kdoc success Errors and warnings before: 0 this patch: 0
netdev/source_inline success Was 0 now: 0

Commit Message

Petr Machata March 22, 2023, 4:49 p.m. UTC 
From: Amit Cohen <amcohen@nvidia.com>

MCAM register reports the device supported management features. Querying
this register exposes if features are supported with the current firmware
version in the current ASIC. Then, the drive can separate between different
implementations dynamically.

MCAM register supports querying whether a new reset flow (which includes
PCI reset) is supported or not. Add support for the register as preparation
for support of the new reset flow.

Note that the access to the bits in the field 'mng_feature_cap_mask' is
not same to other mask fields in other registers. In most of the cases
bit #0 is the first one in the last dword, in MCAM register, bits #0-#31
are in the first dword and so on. Declare the mask field using bits arrays
per dword to simplify the access.

Signed-off-by: Amit Cohen <amcohen@nvidia.com>
Reviewed-by: Petr Machata <petrm@nvidia.com>
Signed-off-by: Petr Machata <petrm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlxsw/reg.h | 74 +++++++++++++++++++++++
 1 file changed, 74 insertions(+)

Comments

Simon Horman March 26, 2023, 2 p.m. UTC | #1 
On Wed, Mar 22, 2023 at 05:49:31PM +0100, Petr Machata wrote:
> From: Amit Cohen <amcohen@nvidia.com>
> 
> MCAM register reports the device supported management features. Querying
> this register exposes if features are supported with the current firmware
> version in the current ASIC. Then, the drive can separate between different
> implementations dynamically.
> 
> MCAM register supports querying whether a new reset flow (which includes
> PCI reset) is supported or not. Add support for the register as preparation
> for support of the new reset flow.
> 
> Note that the access to the bits in the field 'mng_feature_cap_mask' is
> not same to other mask fields in other registers. In most of the cases
> bit #0 is the first one in the last dword, in MCAM register, bits #0-#31
> are in the first dword and so on. Declare the mask field using bits arrays
> per dword to simplify the access.
> 
> Signed-off-by: Amit Cohen <amcohen@nvidia.com>
> Reviewed-by: Petr Machata <petrm@nvidia.com>
> Signed-off-by: Petr Machata <petrm@nvidia.com>

Reviewed-by: Simon Horman <simon.horman@corigine.com>
Simon Horman March 26, 2023, 2:02 p.m. UTC | #2 
On Wed, Mar 22, 2023 at 05:49:31PM +0100, Petr Machata wrote:
> From: Amit Cohen <amcohen@nvidia.com>
> 
> MCAM register reports the device supported management features. Querying
> this register exposes if features are supported with the current firmware
> version in the current ASIC. Then, the drive can separate between different
> implementations dynamically.
> 
> MCAM register supports querying whether a new reset flow (which includes
> PCI reset) is supported or not. Add support for the register as preparation
> for support of the new reset flow.
> 
> Note that the access to the bits in the field 'mng_feature_cap_mask' is
> not same to other mask fields in other registers. In most of the cases
> bit #0 is the first one in the last dword, in MCAM register, bits #0-#31
> are in the first dword and so on. Declare the mask field using bits arrays
> per dword to simplify the access.
> 
> Signed-off-by: Amit Cohen <amcohen@nvidia.com>
> Reviewed-by: Petr Machata <petrm@nvidia.com>
> Signed-off-by: Petr Machata <petrm@nvidia.com>

I'm fine with this patch, and offered a Reviewed-by tag in another email.
But when sending that I forgot the minor nit below.
Please regard it as informational only.

> ---
>  drivers/net/ethernet/mellanox/mlxsw/reg.h | 74 +++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
> 
> diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
> index 0d7d5e28945a..c4446085ebc5 100644
> --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
> +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h

...

> +static inline void
> +mlxsw_reg_mcam_unpack(char *payload,
> +		      enum mlxsw_reg_mcam_mng_feature_cap_mask_bits bit,
> +		      bool *p_mng_feature_cap_val)
> +{
> +	int offset = bit % (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE);
> +	int dword = bit / (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE);

nit: checkpatch seems mildly upset that there is no blank line here.

> +	u8 (*getters[])(const char *, u16) = {
> +		mlxsw_reg_mcam_mng_feature_cap_mask_dw0_get,
> +		mlxsw_reg_mcam_mng_feature_cap_mask_dw1_get,
> +		mlxsw_reg_mcam_mng_feature_cap_mask_dw2_get,
> +		mlxsw_reg_mcam_mng_feature_cap_mask_dw3_get,
> +	};
Petr Machata March 27, 2023, 9:35 a.m. UTC | #3 
Simon Horman <simon.horman@corigine.com> writes:

> On Wed, Mar 22, 2023 at 05:49:31PM +0100, Petr Machata wrote:
>> From: Amit Cohen <amcohen@nvidia.com>
>> 
>> MCAM register reports the device supported management features. Querying
>> this register exposes if features are supported with the current firmware
>> version in the current ASIC. Then, the drive can separate between different
>> implementations dynamically.
>> 
>> MCAM register supports querying whether a new reset flow (which includes
>> PCI reset) is supported or not. Add support for the register as preparation
>> for support of the new reset flow.
>> 
>> Note that the access to the bits in the field 'mng_feature_cap_mask' is
>> not same to other mask fields in other registers. In most of the cases
>> bit #0 is the first one in the last dword, in MCAM register, bits #0-#31
>> are in the first dword and so on. Declare the mask field using bits arrays
>> per dword to simplify the access.
>> 
>> Signed-off-by: Amit Cohen <amcohen@nvidia.com>
>> Reviewed-by: Petr Machata <petrm@nvidia.com>
>> Signed-off-by: Petr Machata <petrm@nvidia.com>
>
> I'm fine with this patch, and offered a Reviewed-by tag in another email.
> But when sending that I forgot the minor nit below.
> Please regard it as informational only.
>
>> ---
>>  drivers/net/ethernet/mellanox/mlxsw/reg.h | 74 +++++++++++++++++++++++
>>  1 file changed, 74 insertions(+)
>> 
>> diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
>> index 0d7d5e28945a..c4446085ebc5 100644
>> --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
>> +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
>
> ...
>
>> +static inline void
>> +mlxsw_reg_mcam_unpack(char *payload,
>> +		      enum mlxsw_reg_mcam_mng_feature_cap_mask_bits bit,
>> +		      bool *p_mng_feature_cap_val)
>> +{
>> +	int offset = bit % (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE);
>> +	int dword = bit / (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE);
>
> nit: checkpatch seems mildly upset that there is no blank line here.

Yes, thanks for pointing this out. I saw that, too. The complaint is
that there should be a blank line after the declaration block, but the
next line is still a part of the declaration block.

>> +	u8 (*getters[])(const char *, u16) = {
>> +		mlxsw_reg_mcam_mng_feature_cap_mask_dw0_get,
>> +		mlxsw_reg_mcam_mng_feature_cap_mask_dw1_get,
>> +		mlxsw_reg_mcam_mng_feature_cap_mask_dw2_get,
>> +		mlxsw_reg_mcam_mng_feature_cap_mask_dw3_get,
>> +	};
Simon Horman March 27, 2023, 9:53 a.m. UTC | #4 
On Mon, Mar 27, 2023 at 11:35:24AM +0200, Petr Machata wrote:
> 
> Simon Horman <simon.horman@corigine.com> writes:
> 
> > On Wed, Mar 22, 2023 at 05:49:31PM +0100, Petr Machata wrote:
> >> From: Amit Cohen <amcohen@nvidia.com>
> >> 
> >> MCAM register reports the device supported management features. Querying
> >> this register exposes if features are supported with the current firmware
> >> version in the current ASIC. Then, the drive can separate between different
> >> implementations dynamically.
> >> 
> >> MCAM register supports querying whether a new reset flow (which includes
> >> PCI reset) is supported or not. Add support for the register as preparation
> >> for support of the new reset flow.
> >> 
> >> Note that the access to the bits in the field 'mng_feature_cap_mask' is
> >> not same to other mask fields in other registers. In most of the cases
> >> bit #0 is the first one in the last dword, in MCAM register, bits #0-#31
> >> are in the first dword and so on. Declare the mask field using bits arrays
> >> per dword to simplify the access.
> >> 
> >> Signed-off-by: Amit Cohen <amcohen@nvidia.com>
> >> Reviewed-by: Petr Machata <petrm@nvidia.com>
> >> Signed-off-by: Petr Machata <petrm@nvidia.com>
> >
> > I'm fine with this patch, and offered a Reviewed-by tag in another email.
> > But when sending that I forgot the minor nit below.
> > Please regard it as informational only.
> >
> >> ---
> >>  drivers/net/ethernet/mellanox/mlxsw/reg.h | 74 +++++++++++++++++++++++
> >>  1 file changed, 74 insertions(+)
> >> 
> >> diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
> >> index 0d7d5e28945a..c4446085ebc5 100644
> >> --- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
> >> +++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
> >
> > ...
> >
> >> +static inline void
> >> +mlxsw_reg_mcam_unpack(char *payload,
> >> +		      enum mlxsw_reg_mcam_mng_feature_cap_mask_bits bit,
> >> +		      bool *p_mng_feature_cap_val)
> >> +{
> >> +	int offset = bit % (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE);
> >> +	int dword = bit / (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE);
> >
> > nit: checkpatch seems mildly upset that there is no blank line here.
> 
> Yes, thanks for pointing this out. I saw that, too. The complaint is
> that there should be a blank line after the declaration block, but the
> next line is still a part of the declaration block.

Yes, right you are.
Sorry for missing that.

> 
> >> +	u8 (*getters[])(const char *, u16) = {
> >> +		mlxsw_reg_mcam_mng_feature_cap_mask_dw0_get,
> >> +		mlxsw_reg_mcam_mng_feature_cap_mask_dw1_get,
> >> +		mlxsw_reg_mcam_mng_feature_cap_mask_dw2_get,
> >> +		mlxsw_reg_mcam_mng_feature_cap_mask_dw3_get,
> >> +	};
>
diff mbox series

Patch

diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
index 0d7d5e28945a..c4446085ebc5 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
@@ -10509,6 +10509,79 @@  static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
 		mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
 }
 
+/* MCAM - Management Capabilities Mask Register
+ * --------------------------------------------
+ * Reports the device supported management features.
+ */
+#define MLXSW_REG_MCAM_ID 0x907F
+#define MLXSW_REG_MCAM_LEN 0x48
+
+MLXSW_REG_DEFINE(mcam, MLXSW_REG_MCAM_ID, MLXSW_REG_MCAM_LEN);
+
+enum mlxsw_reg_mcam_feature_group {
+	/* Enhanced features. */
+	MLXSW_REG_MCAM_FEATURE_GROUP_ENHANCED_FEATURES,
+};
+
+/* reg_mcam_feature_group
+ * Feature list mask index.
+ * Access: Index
+ */
+MLXSW_ITEM32(reg, mcam, feature_group, 0x00, 16, 8);
+
+enum mlxsw_reg_mcam_mng_feature_cap_mask_bits {
+	/* If set, MRSR.command=6 is supported. */
+	MLXSW_REG_MCAM_PCI_RESET = 48,
+};
+
+#define MLXSW_REG_BYTES_PER_DWORD 0x4
+
+/* reg_mcam_mng_feature_cap_mask
+ * Supported port's enhanced features.
+ * Based on feature_group index.
+ * When bit is set, the feature is supported in the device.
+ * Access: RO
+ */
+#define MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(_dw_num, _offset)	 \
+	MLXSW_ITEM_BIT_ARRAY(reg, mcam, mng_feature_cap_mask_dw##_dw_num, \
+			     _offset, MLXSW_REG_BYTES_PER_DWORD, 1)
+
+/* The access to the bits in the field 'mng_feature_cap_mask' is not same to
+ * other mask fields in other registers. In most of the cases bit #0 is the
+ * first one in the last dword. In MCAM register, the first dword contains bits
+ * #0-#31 and so on, so the access to the bits is simpler using bit array per
+ * dword. Declare each dword of 'mng_feature_cap_mask' field separately.
+ */
+MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(0, 0x28);
+MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(1, 0x2C);
+MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(2, 0x30);
+MLXSW_REG_MCAM_MNG_FEATURE_CAP_MASK_DWORD(3, 0x34);
+
+static inline void
+mlxsw_reg_mcam_pack(char *payload, enum mlxsw_reg_mcam_feature_group feat_group)
+{
+	MLXSW_REG_ZERO(mcam, payload);
+	mlxsw_reg_mcam_feature_group_set(payload, feat_group);
+}
+
+static inline void
+mlxsw_reg_mcam_unpack(char *payload,
+		      enum mlxsw_reg_mcam_mng_feature_cap_mask_bits bit,
+		      bool *p_mng_feature_cap_val)
+{
+	int offset = bit % (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE);
+	int dword = bit / (MLXSW_REG_BYTES_PER_DWORD * BITS_PER_BYTE);
+	u8 (*getters[])(const char *, u16) = {
+		mlxsw_reg_mcam_mng_feature_cap_mask_dw0_get,
+		mlxsw_reg_mcam_mng_feature_cap_mask_dw1_get,
+		mlxsw_reg_mcam_mng_feature_cap_mask_dw2_get,
+		mlxsw_reg_mcam_mng_feature_cap_mask_dw3_get,
+	};
+
+	if (!WARN_ON_ONCE(dword >= ARRAY_SIZE(getters)))
+		*p_mng_feature_cap_val = getters[dword](payload, offset);
+}
+
 /* MPSC - Monitoring Packet Sampling Configuration Register
  * --------------------------------------------------------
  * MPSC Register is used to configure the Packet Sampling mechanism.
@@ -12904,6 +12977,7 @@  static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
 	MLXSW_REG(mcqi),
 	MLXSW_REG(mcc),
 	MLXSW_REG(mcda),
+	MLXSW_REG(mcam),
 	MLXSW_REG(mpsc),
 	MLXSW_REG(mgpc),
 	MLXSW_REG(mprs),