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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 11/14] mlxsw: pci: Move software reset code to a separate function Date: Wed, 15 Nov 2023 13:17:20 +0100 Message-ID: <395237a59d495700926cefa8bb713cdd9364fbc7.1700047319.git.petrm@nvidia.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FE:EE_|PH0PR12MB7931:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d12ec4e-76f6-4136-2a6e-08dbe5d535d9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sB/KvxRxYt+xHQS6l95FUawFUXGWV5oTil7tpX/B29XPuSM0GziWBw3d9+C8joPv44Pimh46IjgN6qOm+hTIS098KxwFJW/pAqIZM9scKuQd+vgDhpdowUHS/XdwLabdX3j3pJ2nWziTcttXLE2S555EocwHGvMbx5KMXTpqWzghGdE1bgX3Hj/IO3LjSsBsmuoWLF4ID6EFEb+DTcPQ+RKaV+LK4A5rGEC5CNuYEmRjfd9ue09HaggK0DpQeI9r0ZK/RVZZ8R6twNuq9M8zgo/ShHDBcbESvsfp3aabQfeRt+mBCjs5HjOqDmbKaxnjh2zwvWrKH0DkCXHrT94c4cJjuhun5p1UDRODc8uDBXLBO3GXKwI3kAn3INKFe10RI1Q4QeYHuDaZWXusK+gWs2HsQAmk/xoPnRru+Dw7YWtByWfaAKaHvVYCma/tkZXPCujGKEpNQvVRrpxPchPOPBDtqK+8zls/6/l/Yzw9b4JjlvPiRwbJXZ2o5nOe9ovDSBQbfi5qku5aJxKtnv9k3hGm1HuoSCGRVVe8K7/g1vPP0mS7MA1EmpojrEBKBxoDvRGiK2K2796XG8QaLnjc14NMZNjdB6lzQxjV3VebDCnturBKKmcV970iA2aMcok1bua/ddgJbOnd6TkZ8UORZRxLT/UeNw03qveQ9mn9flbqfNnJovQgwgWfXRpX0ddmvGjPjlKa7eype+fe0C7o1KMM47gTi7Bq3+h8c5Gamyo= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(376002)(39860400002)(396003)(346002)(136003)(230922051799003)(451199024)(1800799009)(82310400011)(186009)(64100799003)(36840700001)(46966006)(40470700004)(86362001)(70206006)(70586007)(40460700003)(478600001)(47076005)(6666004)(82740400003)(54906003)(316002)(110136005)(336012)(426003)(83380400001)(16526019)(7636003)(107886003)(26005)(356005)(2616005)(41300700001)(36860700001)(8676002)(8936002)(2906002)(5660300002)(4326008)(36756003)(40480700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Nov 2023 12:20:09.5245 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2d12ec4e-76f6-4136-2a6e-08dbe5d535d9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7931 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen In general, the existing flow of software reset in the driver is: 1. Wait for system ready status. 2. Send MRSR command, to start the reset. 3. Wait for system ready status. This flow will be extended once a new reset command is supported. As a preparation, move step #2 to a separate function. Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Signed-off-by: Ido Schimmel Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index fe0b8a38d44e..080881c94c5a 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -1476,11 +1476,18 @@ static int mlxsw_pci_sys_ready_wait(struct mlxsw_pci *mlxsw_pci, return -EBUSY; } -static int -mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) +static int mlxsw_pci_reset_sw(struct mlxsw_pci *mlxsw_pci) { - struct pci_dev *pdev = mlxsw_pci->pdev; char mrsr_pl[MLXSW_REG_MRSR_LEN]; + + mlxsw_reg_mrsr_pack(mrsr_pl, MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET); + return mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); +} + +static int +mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) +{ + struct pci_dev *pdev = mlxsw_pci->pdev; u32 sys_status; int err; @@ -1491,8 +1498,7 @@ mlxsw_pci_reset(struct mlxsw_pci *mlxsw_pci, const struct pci_device_id *id) return err; } - mlxsw_reg_mrsr_pack(mrsr_pl, MLXSW_REG_MRSR_COMMAND_SOFTWARE_RESET); - err = mlxsw_reg_write(mlxsw_pci->core, MLXSW_REG(mrsr), mrsr_pl); + err = mlxsw_pci_reset_sw(mlxsw_pci); if (err) return err;