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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 07/12] mlxsw: pci: Add PCI ports array Date: Tue, 4 Feb 2025 12:05:02 +0100 Message-ID: <45fad23a5d21df36ef77b3a5c3e8f9d8e09540f9.1738665783.git.petrm@nvidia.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000E:EE_|CH2PR12MB4247:EE_ X-MS-Office365-Filtering-Correlation-Id: 8dbf0236-4c16-4d23-e94b-08dd450c10ef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: u3JEwqJC4OdJBk5iVyc5wnIP9f4DbtqE7EaUi5zPx+qpaAPlceUt5UUnUY41Pwuku8cUQEdPNxgnXHgTs6EnX8aiYn/dZ67v6wnkejpfbkLhg0ZGsH9RKGcXxqLAGIwnHBzy/2O6lZ1Lk4iJWfnurd0mI9vkCatImFMCnRjBSWe4WmXEtsfht1d7ZNZ8RL4GH0riSJFj7v1LX9RbdSowrZH8QmduzdSjtJdayDVugSxhMrhUuL4vrA84MYgkS6zhVEIh7bqbwPUsXm6KaiPPiNSXbG78+bDNJ53+J6yy3b8yT0YuZWiUT+/VkoA1NrSHw2Vr+DQBsuj7/ue4d0nLdn+lx23hmjaTyeQzcMdxaTysg6ybLhkfB+m8ueSk8eeGk39lBdrsJJW4B/xwm7CxjCSWdThMVPcnxo9g4JVFjLhR4nLIQrNfbOHCmzvLbotQSJL8Ke9kpZN8oBlAB6XT7DfPd2zC3xA8JbnB3xqz2mba8ARyjv4+unzxYDwEGbX910tHIRaj7p8dcA1h5yifaU/xv0a/WDFJzA40bRqOP9Lq5/+CESAf05L2f2Bihp/sH6tUckyhSMxXrMku9/LYjDjwfMIK9fN4OBRdZXsfkev4f/yb4437gP12O6Z1/rC6BLaiMqxsZrdzkDF26YX4Lh25OAaSiZ7SIt7z063AU3njsNQh3EJp7OGfCbNr2YnWys8jdeFM6cnQiOMB6YBqkEo2aIH97q1PXNjewMGVjhzh7AiPZH+KtWrFcqL/GfsNszRdvhLgyUjiCL59Sky47Di8qhH0a5690IvfJkW7vjdXNl+anhAdFlDhg6/SOVOhc6E39J/dFs/zMlMhtkGZDMuq9i1JRSg0+9EoGdFUzWQCz5YBy/i4UJ+7NrPrs89vlDbd9XKWfgkEJmL+do/n90oIBLBSbmFR+9d6nthZjnYW5LHphWLLjQJDnVKRTbfAC5yeGiEEqewUW6AMcnL/NJZNDKa6Z18R2y9CzuHtkitYpbqBYkk9G+zkAuuzH3VtDVjuExHtAPXSe5EE3b44Hf4V/xC9dGsW06xlLhJ+vofUQGDu3+aJ8xPCtZUx/z+nTjxIWIodb6At7P+noGzYEendpCMo/dRlnzOSy9Gxp9kEg0Ku53RxHUO7lJ2O+Jp644frHLU4ktS2FbUtNtVTiU/duCJI/i7I3ciFtJrYxN1hDEGIJZqcrQTfN5O52RgSKZlXARVum5DbAjpAdiq02Ww/CsdbMpohOCgWqfsmU0k7mYj6WvgAYTNCg+GlzaKDKGfnsBoXLM5TStSCS1fwL6yr9mf59YrPTT1wx9WAUxxRR/vqa3dCpyv+kch3eCtwZHUflCTUhVJp3LSfOnDIQiA1nHbm4BUimCRSVw4VI316CQGULuKHOFdLkf34WxEgMKi8q4XEYJ8eiNfdrwTTwvG9KZYWdi3sjdOP9URYVhCYo2PAxiFdWxmZGNuQCwTKdatg4zao0hBN/92zV12Mmr+JJSPgXlJXoBY5gjg93oE= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:07:08.0998 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8dbf0236-4c16-4d23-e94b-08dd450c10ef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4247 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen A future patch set will add support for XDP in mlxsw driver. When a packet is received, the Rx local port is provided by the CQE, and we should check if an XDP program is configured for this port. To allow quick mapping between local port to netdevice and XDP program, add an array of mlxsw_pci_port structure. Allocate the array as part of init, according to maximum number of ports. For now, this structure only contains pointer to netdevice. Next patches will extend the structure. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 8af4050d5fc6..563b9c0578f8 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -102,6 +102,10 @@ struct mlxsw_pci_queue_type_group { u8 count; /* number of queues in group */ }; +struct mlxsw_pci_port { + struct net_device *netdev; +}; + struct mlxsw_pci { struct pci_dev *pdev; u8 __iomem *hw_addr; @@ -138,6 +142,7 @@ struct mlxsw_pci { struct net_device *napi_dev_tx; struct net_device *napi_dev_rx; unsigned int max_ports; + struct mlxsw_pci_port *pci_ports; }; static int mlxsw_pci_napi_devs_init(struct mlxsw_pci *mlxsw_pci) @@ -186,6 +191,24 @@ static int mlxsw_pci_max_ports_set(struct mlxsw_pci *mlxsw_pci) return 0; } +static int mlxsw_pci_ports_init(struct mlxsw_pci *mlxsw_pci) +{ + struct mlxsw_pci_port *pci_ports; + + pci_ports = kcalloc(mlxsw_pci->max_ports, + sizeof(struct mlxsw_pci_port), GFP_KERNEL); + if (!pci_ports) + return -ENOMEM; + + mlxsw_pci->pci_ports = pci_ports; + return 0; +} + +static void mlxsw_pci_ports_fini(struct mlxsw_pci *mlxsw_pci) +{ + kfree(mlxsw_pci->pci_ports); +} + static char *__mlxsw_pci_queue_elem_get(struct mlxsw_pci_queue *q, size_t elem_size, int elem_index) { @@ -2088,6 +2111,10 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, if (err) goto err_max_ports_set; + err = mlxsw_pci_ports_init(mlxsw_pci); + if (err) + goto err_ports_init; + err = mlxsw_pci_aqs_init(mlxsw_pci, mbox); if (err) goto err_aqs_init; @@ -2105,6 +2132,8 @@ static int mlxsw_pci_init(void *bus_priv, struct mlxsw_core *mlxsw_core, err_request_eq_irq: mlxsw_pci_aqs_fini(mlxsw_pci); err_aqs_init: + mlxsw_pci_ports_fini(mlxsw_pci); +err_ports_init: err_max_ports_set: mlxsw_pci_napi_devs_fini(mlxsw_pci); err_napi_devs_init: @@ -2135,6 +2164,7 @@ static void mlxsw_pci_fini(void *bus_priv) free_irq(pci_irq_vector(mlxsw_pci->pdev, 0), mlxsw_pci); mlxsw_pci_aqs_fini(mlxsw_pci); + mlxsw_pci_ports_fini(mlxsw_pci); mlxsw_pci_napi_devs_fini(mlxsw_pci); mlxsw_pci_fw_area_fini(mlxsw_pci); mlxsw_pci_free_irq_vectors(mlxsw_pci);