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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 1/5] mlxsw: pci: Handle up to 64 Rx completions in tasklet Date: Fri, 26 Apr 2024 14:42:22 +0200 Message-ID: <5381c00c284ddc62d90dc88f3b080bf701544d94.1714134205.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE39:EE_|DM6PR12MB4042:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e69572b-4c9f-4532-4a73-08dc65eeb2fe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|36860700004|1800799015|82310400014|376005; X-Microsoft-Antispam-Message-Info: kIeAquW/XoeahTwGb/PFRUCf0VflQf6cX4o7/FwVY75IqcfuW5tZbw/ULFyBUEkqsm7tDX4UDAwtCl8dBCtddZEtSAqPQDT9P/8/P+q+5mrnNgBC10S0TGm047lRX1dF7+VYluXX7nA+ccME0/PZLoDppO7VyLKXwW2T/rCutI7kCJ/kWe4dJKU7ox4ZK9WEfcb/5m0L6ocOqzHBENr/emCh/1HODD9QgxklfHi8dilDEPNty2sv6vZwajsLHQE5RaH80XGFQBqtdjEkVkpT9WTQq1p8vxUCvv6OiQx9Oh8dX9tTp+4p62uWJP619fZMZlUinqRggMHbTGSSTOqwnGZDXZGI/RQGBUsSd7IyY7H+yGBFW4HKpTX7Vy5FNL3uyYiLSOjwvXuMi4Up7CADCBxmDzVzcn9GPuvXBh2o83SBbRdEktf2QdxsbeyMt/O3KXVAxmEBmrjbyX0D2/+UuRJ6gCGLu0ruVravDqUjNEYrH2hWj6topaSYJMLV70sv6C75CnyC8VLpkQAoeYp/kWsRAPZdIjeIo1yqFCIo5vNyOfUUiaxS2zL0XeeHTvpA0r7qT4C/ucecol/nNOyAd5bMlAB6LwQNV9epV/CMZzUn2/1WCWmWIQ9ld3dzj/EnAYStcQTiM36+BGKUDQ0ykKQcKFz70X6AwezG0JNpZpQ0g84jjIQSb63OnM0dfHZymth+BhsPzn9DIUGk5XoJn6jmFbUpE15FOUpRdJtNg+XXK9GARrozNAwWo6ZWDxO1nLguQnXkBr9nue3T2djT5epJq22epXt84joHQN11S2d47yKRV4i3v+d3bN5houfOzDutJCDyS2qkAP9tpoGaUijz7XU50Cep8wVC1Rh17oUO9HuNZ2TrW45MzeQ80o0nJ34IiMkpdPAaw5rmU4a+i/6yovCGFNKsYFuHzatd/tmAIERn5IWqTgP2b16q7Ky7851jNR2bWGMlHciAY8j86jYzJ1o9weRCwKImsOa26GlhfzbB82QCfe2l0dE9DM1Ibyd0l3KhocXZTXe0gBuKeBXt1E29rWCwDu1lYBeA6HZXsfOt00rFLM6/6zFjDDpbc7SD4YJhDhOFYKFwQFPSp/P/niCYfVTJKASQgkiGpaTMxoNpXW3N4E5OTLAPQBgeZ/x5GlVzOmw9DG+8xMOh42Oecc3N3im9y0tqtgLnHH5e1FFTTlFPV9ZuXK/6KPH8V9Qrl/hHnE526cvCaTtqxO+4sGduPzSGD3Juz/WXN6CiMECqPML2q7omsbxodm3IBA4bpVkw+qymSmydpgZuW6BVhhgC+yM89UF4d2N/tWVaBAaIYDXQaB0Ermoyi9yQexQqEaBrJK+vXWDfQcotshwUEzH2wQVFV2UCmOUylzjyPvVLrayPQOqc5FU7PwQ+ X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(1800799015)(82310400014)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2024 12:45:05.8305 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7e69572b-4c9f-4532-4a73-08dc65eeb2fe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE39.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4042 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen We can get many completions in one interrupt. Currently, the CQ tasklet handles up to half queue size completions, and then arms the hardware to generate additional events, which means that in case that there were additional completions that we did not handle, we will get immediately an additional interrupt to handle the rest. The decision to handle up to half of the queue size is arbitrary and was determined in 2015, when mlxsw driver was added to the kernel. One additional fact that should be taken into account is that while WQEs from RDQ are handled, the CPU that handles the tasklet is dedicated for this task, which means that we might hold the CPU for a long time. Handle WQEs in smaller chucks, then arm CQ doorbell to notify the hardware to send additional notifications. Set the chunk size to 64 as this number is recommended using NAPI and the driver will use NAPI in a next patch. Note that for now we use ARM doorbell to retrigger CQ tasklet, but with NAPI it will be more efficient as software will reschedule the poll method and we will not involve hardware for that. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 13fd067c39ed..8668947400ab 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -652,12 +652,13 @@ static char *mlxsw_pci_cq_sw_cqe_get(struct mlxsw_pci_queue *q) return elem; } +#define MLXSW_PCI_CQ_MAX_HANDLE 64 + static void mlxsw_pci_cq_rx_tasklet(struct tasklet_struct *t) { struct mlxsw_pci_queue *q = from_tasklet(q, t, tasklet); struct mlxsw_pci_queue *rdq = q->cq.dq; struct mlxsw_pci *mlxsw_pci = q->pci; - int credits = q->count >> 1; int items = 0; char *cqe; @@ -683,7 +684,7 @@ static void mlxsw_pci_cq_rx_tasklet(struct tasklet_struct *t) mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq, wqe_counter, q->cq.v, ncqe); - if (++items == credits) + if (++items == MLXSW_PCI_CQ_MAX_HANDLE) break; }