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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 3/6] mlxsw: spectrum: Query max_lag once Date: Fri, 26 Jan 2024 19:58:28 +0100 Message-ID: <5bfdfa5f8df8ef0211649f08d508b631d104d214.1706293430.git.petrm@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD5:EE_|PH7PR12MB6936:EE_ X-MS-Office365-Filtering-Correlation-Id: 46d3fdfb-2e2c-4e80-a302-08dc1ea0e2e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tGNEI/qzlAky5znagRjEQOXsjvetUGhcNHT3bZs6ZqOTm0eGOORPXzRBSV4Yz1mndCx9iTI/0pkNKOE3+3aqvtN2WLN8drPBjaZiKXcBk//JijRF4zQGcjgbDP7+fvDx8QuK7+4i00rvShSmYVeWK+g1g/aA2jvDjhQWmb3wOTHU+xtKK6gDb6G8mgTCsMl1cfM6DYhssKqf0uHmqEM2CAdQSOthBZz/C+Am+P6FDduoNGbX2BNS0ditN8BD1WyeggsgzqKdqvwXV4i6868S/5fzS+KxvFjjLoPu3l4105FYGbN97+bxj9oXO+TzTik88A+mdv99H/HLLIDleYhePwuEkBUlrLIre527HEMH7cKmRUJy5E39o40WPO/wmxYwpwp0aIPIgRKYNI3+rnE5fc3SAgba8yUxy4kPlJtDz6meX6f0k54lGC6KRcKStRRmh7BvC1RkjI+ly1X4y6dNrh0fE+PqDwLDrdRfCM1GKTAYVY9cC5jsNp/+b1x/trPC7LpynWEc9HCSMh1/3hEu/rp1YZNNRR+JtA0ix/aH7ossv53ESVRygQHrP220CcVIWh5JlRaujefyBczW82XmUIVW960dDjRaL8gkuIH34enN5IyvvVcik5lktchGfW1EL8QQfydB2/c3ojyzFNfdC5q0SoJKcmBkU61CLMi+CTjG3OKg4SDq0MM1awifpjOK5vc/RU9dWkK8NMG1LaqHiOTNBWzLzgdqBFGfQWz6RH3Liuoe01Xzf65WF7xakZyf X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(346002)(136003)(376002)(396003)(230922051799003)(451199024)(64100799003)(82310400011)(186009)(1800799012)(46966006)(36840700001)(40470700004)(5660300002)(6666004)(2906002)(478600001)(4326008)(8676002)(8936002)(316002)(86362001)(70206006)(54906003)(70586007)(110136005)(356005)(336012)(426003)(40460700003)(40480700001)(26005)(16526019)(107886003)(47076005)(83380400001)(36860700001)(7636003)(36756003)(2616005)(41300700001)(82740400003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2024 18:59:12.7906 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 46d3fdfb-2e2c-4e80-a302-08dc1ea0e2e3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6936 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen The maximum number of LAGs is queried from core several times. It is used to allocate LAG array, and then to iterate over it. In addition, it is used for PGT initialization. To simplify the code, instead of querying it several times, store the value as part of 'mlxsw_sp' and use it. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Ido Schimmel Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- .../net/ethernet/mellanox/mlxsw/spectrum.c | 32 ++++--------------- .../net/ethernet/mellanox/mlxsw/spectrum.h | 1 + 2 files changed, 8 insertions(+), 25 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c index ff52028a957b..75fea062a984 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.c +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.c @@ -2695,23 +2695,18 @@ static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp) static int mlxsw_sp_lag_pgt_init(struct mlxsw_sp *mlxsw_sp) { char sgcr_pl[MLXSW_REG_SGCR_LEN]; - u16 max_lag; int err; if (mlxsw_core_lag_mode(mlxsw_sp->core) != MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW) return 0; - err = mlxsw_core_max_lag(mlxsw_sp->core, &max_lag); - if (err) - return err; - /* In DDD mode, which we by default use, each LAG entry is 8 PGT * entries. The LAG table address needs to be 8-aligned, but that ought * to be the case, since the LAG table is allocated first. */ err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, &mlxsw_sp->lag_pgt_base, - max_lag * 8); + mlxsw_sp->max_lag * 8); if (err) return err; if (WARN_ON_ONCE(mlxsw_sp->lag_pgt_base % 8)) { @@ -2728,25 +2723,18 @@ static int mlxsw_sp_lag_pgt_init(struct mlxsw_sp *mlxsw_sp) err_mid_alloc_range: mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base, - max_lag * 8); + mlxsw_sp->max_lag * 8); return err; } static void mlxsw_sp_lag_pgt_fini(struct mlxsw_sp *mlxsw_sp) { - u16 max_lag; - int err; - if (mlxsw_core_lag_mode(mlxsw_sp->core) != MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW) return; - err = mlxsw_core_max_lag(mlxsw_sp->core, &max_lag); - if (err) - return; - mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base, - max_lag * 8); + mlxsw_sp->max_lag * 8); } #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe @@ -2759,7 +2747,6 @@ struct mlxsw_sp_lag { static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) { char slcr_pl[MLXSW_REG_SLCR_LEN]; - u16 max_lag; u32 seed; int err; @@ -2778,7 +2765,7 @@ static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) if (err) return err; - err = mlxsw_core_max_lag(mlxsw_sp->core, &max_lag); + err = mlxsw_core_max_lag(mlxsw_sp->core, &mlxsw_sp->max_lag); if (err) return err; @@ -2789,7 +2776,7 @@ static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp) if (err) return err; - mlxsw_sp->lags = kcalloc(max_lag, sizeof(struct mlxsw_sp_lag), + mlxsw_sp->lags = kcalloc(mlxsw_sp->max_lag, sizeof(struct mlxsw_sp_lag), GFP_KERNEL); if (!mlxsw_sp->lags) { err = -ENOMEM; @@ -4340,14 +4327,9 @@ static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp, { struct mlxsw_sp_lag *lag; int free_lag_id = -1; - u16 max_lag; - int err, i; + int i; - err = mlxsw_core_max_lag(mlxsw_sp->core, &max_lag); - if (err) - return err; - - for (i = 0; i < max_lag; i++) { + for (i = 0; i < mlxsw_sp->max_lag; i++) { lag = &mlxsw_sp->lags[i]; if (lag->ref_count) { if (lag->dev == lag_dev) { diff --git a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h index dd2f05a6d909..898d24232935 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/spectrum.h +++ b/drivers/net/ethernet/mellanox/mlxsw/spectrum.h @@ -161,6 +161,7 @@ struct mlxsw_sp { unsigned char base_mac[ETH_ALEN]; const unsigned char *mac_mask; struct mlxsw_sp_lag *lags; + u16 max_lag; struct mlxsw_sp_port_mapping *port_mapping; struct mlxsw_sp_port_mapping_events port_mapping_events; struct rhashtable sample_trigger_ht;