@@ -479,8 +479,14 @@ static int dwegmac_get_hw_feature(struct stmmac_priv *priv,
dma_cap->rx_coe_type2 = (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
dma_cap->rxfifo_over_2048 = (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
/* TX and RX number of channels */
- dma_cap->number_rx_channel = (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
- dma_cap->number_tx_channel = (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
+ if (FIELD_GET(DWEGMAC_FIX_CHANNEL_NUM, priv->plat->dwegmac_flags) &&
+ ((hw_cap & (DMA_HW_FEAT_RXCHCNT | DMA_HW_FEAT_TXCHCNT)) >> 20) == 0) {
+ dma_cap->number_rx_channel = 8;
+ dma_cap->number_tx_channel = 8;
+ } else {
+ dma_cap->number_rx_channel = (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
+ dma_cap->number_tx_channel = (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
+ }
/* Alternate (enhanced) DESC mode */
dma_cap->enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
@@ -175,6 +175,7 @@ static int loongson_gmac_config(struct pci_dev *pdev,
switch (version & 0xff) {
case DWEGMAC_CORE_1_00:
ret = loongson_dwmac_config_multi_msi(pdev, plat, res, np, 8);
+ plat->dwegmac_flags |= FIELD_PREP(DWEGMAC_FIX_CHANNEL_NUM, 1);
break;
default:
ret = loongson_dwmac_config_single_irq(pdev, plat, res, np);
@@ -14,6 +14,8 @@
#include <linux/platform_device.h>
#include <linux/phy.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
#define MTL_MAX_RX_QUEUES 8
#define MTL_MAX_TX_QUEUES 8
@@ -205,6 +207,8 @@ struct dwmac4_addrs {
u32 mtl_low_cred_offset;
};
+#define DWEGMAC_FIX_CHANNEL_NUM BIT(0)
+
struct plat_stmmacenet_data {
int bus_id;
int phy_addr;
@@ -297,5 +301,6 @@ struct plat_stmmacenet_data {
bool has_integrated_pcs;
int has_egmac;
u32 irq_flags;
+ unsigned int dwegmac_flags;
};
#endif