| Message ID | 66032a4e2093ef82d2035966212c5a2ef2b6fdc9.1690762860.git.daniel@makrotopia.org (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [net-next,v2] net: ethernet: mtk_eth_soc: support per-flow accounting on MT7988 | expand |
On Mon, Jul 31, 2023 at 01:24:22AM +0100, Daniel Golle wrote: > NETSYS_V3 uses 64 bits for each counters while older SoCs were using > 48 bits for each counter. > Support reading per-flow byte and package counters on NETSYS_V3. > > Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Larysa Zaremba <larysa.zaremba@intel.com> > --- > v2: fix typo bytes_cnt_* -> byte_cnt_* > > drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 + > drivers/net/ethernet/mediatek/mtk_ppe.c | 18 ++++++++++++++---- > drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 2 ++ > 3 files changed, 17 insertions(+), 4 deletions(-) > > diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c > index 05be702f19c5e..1b89f800f6dff 100644 > --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c > +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c > @@ -5064,6 +5064,7 @@ static const struct mtk_soc_data mt7988_data = { > .version = 3, > .offload_version = 2, > .hash_offset = 4, > + .has_accounting = true, > .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, > .txrx = { > .txd_size = sizeof(struct mtk_tx_dma_v2), > diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c > index bf1ecb0c1c109..dd2df32b29c3b 100644 > --- a/drivers/net/ethernet/mediatek/mtk_ppe.c > +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c > @@ -107,10 +107,20 @@ static int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *p > cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1); > cnt_r2 = readl(ppe->base + MTK_PPE_MIB_SER_R2); > > - byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); > - byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); > - pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); > - pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); > + if (mtk_is_netsys_v3_or_greater(ppe->eth)) { Would be more readable with u32 cnt_r3 = readl(ppe->base + MTK_PPE_MIB_SER_R3); > + /* 64 bit for each counter */ > + byte_cnt_low = cnt_r0; > + byte_cnt_high = cnt_r1; > + pkt_cnt_low = cnt_r2; and pkt_cnt_high = cnt_r3; But looks fine as it is. > + pkt_cnt_high = readl(ppe->base + MTK_PPE_MIB_SER_R3); > + } else { > + /* 48 bit for each counter */ > + byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); > + byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); > + pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); > + pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); > + } > + > *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low; > *packets = (pkt_cnt_high << 16) | pkt_cnt_low; > > diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h > index a2e61b3eb006d..3ce088eef0efd 100644 > --- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h > +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h > @@ -163,6 +163,8 @@ enum { > #define MTK_PPE_MIB_SER_R2 0x348 > #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH GENMASK(23, 0) > > +#define MTK_PPE_MIB_SER_R3 0x34c > + > #define MTK_PPE_MIB_CACHE_CTL 0x350 > #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0) > #define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2) > -- > 2.41.0 > >
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 05be702f19c5e..1b89f800f6dff 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -5064,6 +5064,7 @@ static const struct mtk_soc_data mt7988_data = { .version = 3, .offload_version = 2, .hash_offset = 4, + .has_accounting = true, .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE, .txrx = { .txd_size = sizeof(struct mtk_tx_dma_v2), diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c index bf1ecb0c1c109..dd2df32b29c3b 100644 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c @@ -107,10 +107,20 @@ static int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *p cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1); cnt_r2 = readl(ppe->base + MTK_PPE_MIB_SER_R2); - byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); - byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); - pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); - pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); + if (mtk_is_netsys_v3_or_greater(ppe->eth)) { + /* 64 bit for each counter */ + byte_cnt_low = cnt_r0; + byte_cnt_high = cnt_r1; + pkt_cnt_low = cnt_r2; + pkt_cnt_high = readl(ppe->base + MTK_PPE_MIB_SER_R3); + } else { + /* 48 bit for each counter */ + byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0); + byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1); + pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1); + pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2); + } + *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low; *packets = (pkt_cnt_high << 16) | pkt_cnt_low; diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h index a2e61b3eb006d..3ce088eef0efd 100644 --- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h @@ -163,6 +163,8 @@ enum { #define MTK_PPE_MIB_SER_R2 0x348 #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH GENMASK(23, 0) +#define MTK_PPE_MIB_SER_R3 0x34c + #define MTK_PPE_MIB_CACHE_CTL 0x350 #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0) #define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2)
NETSYS_V3 uses 64 bits for each counters while older SoCs were using 48 bits for each counter. Support reading per-flow byte and package counters on NETSYS_V3. Signed-off-by: Daniel Golle <daniel@makrotopia.org> --- v2: fix typo bytes_cnt_* -> byte_cnt_* drivers/net/ethernet/mediatek/mtk_eth_soc.c | 1 + drivers/net/ethernet/mediatek/mtk_ppe.c | 18 ++++++++++++++---- drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 2 ++ 3 files changed, 17 insertions(+), 4 deletions(-)