| Message ID | 6f0ac42c1b60db318b7d746254a9b310dd03aa32.1712917541.git.siyanteng@loongson.cn (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | stmmac: Add Loongson platform support | expand |
On Fri, Apr 12, 2024 at 07:28:49PM +0800, Yanteng Si wrote: > Based on IP core classification, loongson has two types of network > devices: GMAC and GNET. GMAC's ip_core id is 0x35/0x37, while GNET's > ip_core id is 0x37/0x10. > > Device tables: > > device type pci_id ip_core > ls2k1000 gmac 7a03 0x35/0x37 > ls7a1000 gmac 7a03 0x35/0x37 > ls2k2000 gnet 7a13 0x10 > ls7a2000 gnet 7a13 0x37 > > The ref/ptp clock of gmac is 125000000. gmac device only > has a MAC chip inside and needs an external PHY chip; > > Signed-off-by: Feiyang Chen <chenfeiyang@loongson.cn> > Signed-off-by: Yinggang Gu <guyinggang@loongson.cn> > Signed-off-by: Yanteng Si <siyanteng@loongson.cn> > --- > .../ethernet/stmicro/stmmac/dwmac-loongson.c | 21 +++++++++++++------ > 1 file changed, 15 insertions(+), 6 deletions(-) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c > index 995c9bd144e0..ad19b4087974 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c > @@ -9,7 +9,8 @@ > #include <linux/of_irq.h> > #include "stmmac.h" > > -static int loongson_default_data(struct plat_stmmacenet_data *plat) > +static void loongson_default_data(struct pci_dev *pdev, > + struct plat_stmmacenet_data *plat) > { > plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ > plat->has_gmac = 1; > @@ -24,16 +25,18 @@ static int loongson_default_data(struct plat_stmmacenet_data *plat) > /* Set the maxmtu to a default of JUMBO_LEN */ > plat->maxmtu = JUMBO_LEN; > > - /* Set default number of RX and TX queues to use */ > - plat->tx_queues_to_use = 1; > - plat->rx_queues_to_use = 1; > - > /* Disable Priority config by default */ > plat->tx_queues_cfg[0].use_prio = false; > plat->rx_queues_cfg[0].use_prio = false; > > /* Disable RX queues routing by default */ > plat->rx_queues_cfg[0].pkt_route = 0x0; > +} > + > +static int loongson_gmac_data(struct pci_dev *pdev, > + struct plat_stmmacenet_data *plat) > +{ > + loongson_default_data(pdev, plat); > > /* Default to phy auto-detection */ > plat->phy_addr = -1; > @@ -42,6 +45,12 @@ static int loongson_default_data(struct plat_stmmacenet_data *plat) > plat->dma_cfg->pblx8 = true; > > plat->multicast_filter_bins = 256; > + plat->clk_ref_rate = 125000000; > + plat->clk_ptp_rate = 125000000; This change is unrelated to the rest of the changes in this patch. Please split the patch up into two: 1. Add ref and ptp clocks for Loongson GMAC 2. Split up the platform data initialization First one is a new feature adding the actual ref clock rates to the driver. The second patch is a preparation before adding the full PCI support. -Serge(y) > + > + plat->tx_queues_to_use = 1; > + plat->rx_queues_to_use = 1; > + > return 0; > } > > @@ -114,7 +123,7 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id > > pci_set_master(pdev); > > - loongson_default_data(plat); > + loongson_gmac_data(pdev, plat); > pci_enable_msi(pdev); > memset(&res, 0, sizeof(res)); > res.addr = pcim_iomap_table(pdev)[0]; > -- > 2.31.4 >
在 2024/4/18 20:26, Serge Semin 写道: >> plat->multicast_filter_bins = 256; >> + plat->clk_ref_rate = 125000000; >> + plat->clk_ptp_rate = 125000000; > This change is unrelated to the rest of the changes in this patch. > Please split the patch up into two: > 1. Add ref and ptp clocks for Loongson GMAC > 2. Split up the platform data initialization > First one is a new feature adding the actual ref clock rates to the > driver. The second patch is a preparation before adding the full PCI > support. > Ok, but we need to reverse the order: 1. Split up the platform data initialization 2. Add ref and ptp clocks for Loongson GMAC Since loongson_gmac_data() needs to be introduced first, then we can add the clock rates of GMAC. Thanks, Yanteng
Hi all 在 2024/4/12 19:28, Yanteng Si 写道: > @@ -42,6 +45,12 @@ static int loongson_default_data(struct plat_stmmacenet_data *plat) > plat->dma_cfg->pblx8 = true; > > plat->multicast_filter_bins = 256; > + plat->clk_ref_rate = 125000000; > + plat->clk_ptp_rate = 125000000; > + > + plat->tx_queues_to_use = 1; > + plat->rx_queues_to_use = 1; Sorry, I forgot to delete them. This part of the code has been moved to loongson_dwmac_probe() in this patch set, Why? Because we have two different gnet devices: the 2k2000 supports multiple channels, the 7a2000 only supports single channels, and all GMAC devices only support single channels. If we keep this part of the code here, we will get GMAC_VERSION again in gnet_data() to distinguish them, which will make the code more complex. We can use GMAC_VERSION in probe to distinguish them easily. so the patch will be redesigned in v12. Thanks, Yanteng
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c index 995c9bd144e0..ad19b4087974 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c @@ -9,7 +9,8 @@ #include <linux/of_irq.h> #include "stmmac.h" -static int loongson_default_data(struct plat_stmmacenet_data *plat) +static void loongson_default_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) { plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ plat->has_gmac = 1; @@ -24,16 +25,18 @@ static int loongson_default_data(struct plat_stmmacenet_data *plat) /* Set the maxmtu to a default of JUMBO_LEN */ plat->maxmtu = JUMBO_LEN; - /* Set default number of RX and TX queues to use */ - plat->tx_queues_to_use = 1; - plat->rx_queues_to_use = 1; - /* Disable Priority config by default */ plat->tx_queues_cfg[0].use_prio = false; plat->rx_queues_cfg[0].use_prio = false; /* Disable RX queues routing by default */ plat->rx_queues_cfg[0].pkt_route = 0x0; +} + +static int loongson_gmac_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) +{ + loongson_default_data(pdev, plat); /* Default to phy auto-detection */ plat->phy_addr = -1; @@ -42,6 +45,12 @@ static int loongson_default_data(struct plat_stmmacenet_data *plat) plat->dma_cfg->pblx8 = true; plat->multicast_filter_bins = 256; + plat->clk_ref_rate = 125000000; + plat->clk_ptp_rate = 125000000; + + plat->tx_queues_to_use = 1; + plat->rx_queues_to_use = 1; + return 0; } @@ -114,7 +123,7 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id pci_set_master(pdev); - loongson_default_data(plat); + loongson_gmac_data(pdev, plat); pci_enable_msi(pdev); memset(&res, 0, sizeof(res)); res.addr = pcim_iomap_table(pdev)[0];