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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , CC: Amit Cohen , Ido Schimmel , "Petr Machata" , Alexei Starovoitov , "Daniel Borkmann" , Jesper Dangaard Brouer , John Fastabend , , Subject: [PATCH net-next 05/12] mlxsw: pci: Add a separate function for syncing buffers for CPU Date: Tue, 4 Feb 2025 12:05:00 +0100 Message-ID: <7674318d47d36fb91a64351ca64a491ec61d5284.1738665783.git.petrm@nvidia.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B3:EE_|SA1PR12MB7344:EE_ X-MS-Office365-Filtering-Correlation-Id: 3bc2ce18-b815-4690-6095-08dd450c0807 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: 2TK/K3P5epWp/BWapbqR8ZtEtKK24A3CbPKHxeD30Z+BReRtQK5Q50Zy1+YaicOuNTdiwiwmsQPFSemSLFqW0EvjWvQx4PNYG8lyyDxiteyOxe3aVeOTbaOn6eHbqzawiVUNKm2Eg4MnIwttzy4yKs1X705Lf+e76F48ho0gicF0BWllmXNRcf+wO7Vxu9SQJoPF+IwrcQbrQ6evayiosU73TO72aD3sUZeXGNHxotSibHh+PdkEsEqZoOrnJAFFKWokAMvPNPy7ElvunlivGkzep7aP8pDxeW2NXKpqy9uOcvZcpbqhNcVMat3a5CCWaSGIj5q3cKIGqehan+PO8qUIWUpI1q4YvgwNkgd8Ibf42phJUEsv7k5EgvzrD68Tat9fnS/QHFnMjxBA5nWXkAAYh5gj9EJAylg2LlyJtVOaPHAEXLP+EcQuttaza8g7LvBvJnwQEGYEYVSHzqEZfsHmU/Arb1NsWlKsI0MF02jWugHtnBvVCJ1o1J4l5a8zbs4U3SQhqJusotakXbrfFq4xjjsgxJer5g4gD1ZfTuGYKMZLrvO3uviX7qFbcB/6OInAgSrD6oT1kwmORMOXf8pSV1wNeJyECNcKlwT6frzsiowc9VoldCsoOET7yfQ8pROkQ3Y3wl9O9QKi+pSbniV5d/VYmXnFtQ+HMcFdvgTFnv7zG3ErVZHV6JdHJNcDhZqWKyR2LyJPb12szLo5Gr2buGulKeO+Alplb1seuNNe6wg9HGLcTtvt6ByodXkrKDOjr986tucslwX5359pwRQvv2lYEfX/DPBZcjG+B7jhh6mFbeycFNrXgM9kpS6p/9GHAFZFQOVO8eN08zLaQGshVmz6nfrvYbB7V7YuElL675eFBCTQn/cmKnq7gPYtFhVTfd7nHFfxemyyR0OSZ3NecpLkRV5Vo0fFtPjBzxUVZJnmLtv4zKaDp5zrEFtDLwYVyACXtuVExRCtE6U1ObDs4sa/jn4B9w/oS3T1duR4m8PxH8L3W3HNpOsYbbLic51jFhWTa9myMxcBa64IAx4F9Y21mjt8i0rX4MCDfwIz7cGj6uxn7IB9zxrZcKxgGRmIXrbpjTwaIBT560+rBNFaOmcvflZoZ4698LQ3wTBLI0orV4DxhrJClaIoxiPCNw9bL7u/OemctLWn6lzaSRCJqFRzjNZnRZzlonxKac4eShZUrAw4V5G/Zacp4RIoyTFV3J86mPXh8pT7axHXsaSUvSyDOFFi1/J6lw+k7arfr2z3TLhUYefAFBlFrFFD+lYx9ZYwFEyy4dvtOCh8h5r31PhFjPc8t6XPDgOz1HtNPPH4U31i5LN0jVPJJUBxunK5UoTOt0Ty4V6ZeMhcBBZsOguya5fI85wfiV8jywaqkvQc4/QXxmfWxgP9NbLRids0cryzoiNNT4/JrCVTygY6wtC9gEHUtmACoW4PjDWqev4jQaFqH8Qt8Oec0I9vXSTHmApc5pCykdI0uUPfnNSEJiBfA30NEY31l0T2Qqo= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2025 11:06:53.1541 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3bc2ce18-b815-4690-6095-08dd450c0807 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7344 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen Currently, sync for CPU is done as part of building SKB. When XDP will be supported, such sync should be done earlier, before creating XDP buffer. Add a function for syncing buffers for CPU and call it early in mlxsw_pci_cqe_rdq_handle(), as in future patch, the driver will handle XDP there. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 30 +++++++++++++++++------ 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 374b3f2f117d..5796d836a7ee 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -433,22 +433,34 @@ mlxsw_pci_rx_pkt_info_init(const struct mlxsw_pci *pci, return 0; } +static void +mlxsw_pci_sync_for_cpu(const struct mlxsw_pci_queue *q, + const struct mlxsw_pci_rx_pkt_info *rx_pkt_info) +{ + struct mlxsw_pci_queue *cq = q->u.rdq.cq; + struct page_pool *page_pool; + int i; + + page_pool = cq->u.cq.page_pool; + + for (i = 0; i < rx_pkt_info->num_sg_entries; i++) { + u32 offset = i ? 0 : MLXSW_PCI_SKB_HEADROOM; + + page_pool_dma_sync_for_cpu(page_pool, rx_pkt_info->pages[i], + offset, + rx_pkt_info->sg_entries_size[i]); + } +} + static struct sk_buff * mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, const struct mlxsw_pci_rx_pkt_info *rx_pkt_info) { - struct mlxsw_pci_queue *cq = q->u.rdq.cq; unsigned int linear_data_size; - struct page_pool *page_pool; struct sk_buff *skb; void *data; int i; - linear_data_size = rx_pkt_info->sg_entries_size[0]; - page_pool = cq->u.cq.page_pool; - page_pool_dma_sync_for_cpu(page_pool, rx_pkt_info->pages[0], - MLXSW_PCI_SKB_HEADROOM, linear_data_size); - data = page_address(rx_pkt_info->pages[0]); net_prefetch(data); @@ -457,6 +469,7 @@ mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, return ERR_PTR(-ENOMEM); skb_reserve(skb, MLXSW_PCI_SKB_HEADROOM); + linear_data_size = rx_pkt_info->sg_entries_size[0]; skb_put(skb, linear_data_size); if (rx_pkt_info->num_sg_entries == 1) @@ -468,7 +481,6 @@ mlxsw_pci_rdq_build_skb(struct mlxsw_pci_queue *q, page = rx_pkt_info->pages[i]; frag_size = rx_pkt_info->sg_entries_size[i]; - page_pool_dma_sync_for_cpu(page_pool, page, 0, frag_size); skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 0, frag_size, PAGE_SIZE); } @@ -784,6 +796,8 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, if (err) goto out; + mlxsw_pci_sync_for_cpu(q, &rx_pkt_info); + err = mlxsw_pci_rdq_pages_alloc(q, elem_info, rx_pkt_info.num_sg_entries); if (err)