@@ -216,6 +216,7 @@ static const struct stmmac_hwif_entry {
.tc = &dwmac510_tc_ops,
.mmc = &dwmac_mmc_ops,
.est = &dwmac510_est_ops,
+ .fpe = &dwmac4_fpe_ops,
.setup = dwmac4_setup,
.quirks = NULL,
}, {
@@ -236,6 +237,7 @@ static const struct stmmac_hwif_entry {
.tc = &dwmac510_tc_ops,
.mmc = &dwmac_mmc_ops,
.est = &dwmac510_est_ops,
+ .fpe = &dwmac4_fpe_ops,
.setup = dwmac4_setup,
.quirks = NULL,
}, {
@@ -685,6 +685,7 @@ extern const struct stmmac_desc_ops dwxgmac210_desc_ops;
extern const struct stmmac_mmc_ops dwmac_mmc_ops;
extern const struct stmmac_mmc_ops dwxgmac_mmc_ops;
extern const struct stmmac_est_ops dwmac510_est_ops;
+extern const struct stmmac_fpe_ops dwmac4_fpe_ops;
#define GMAC_VERSION 0x00000020 /* GMAC CORE Version */
#define GMAC4_VERSION 0x00000110 /* GMAC4+ CORE Version */
@@ -6,4 +6,89 @@
#include "stmmac.h"
#include "stmmac_fpe.h"
+#include "dwmac4.h"
+static int __fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)
+{
+ u32 value;
+ int status;
+
+ status = FPE_EVENT_UNKNOWN;
+
+ /* Reads from the MAC_FPE_CTRL_STS register should only be performed
+ * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read"
+ */
+ value = readl(ioaddr);
+
+ if (value & FPE_CTRL_STS_TRSP) {
+ status |= FPE_EVENT_TRSP;
+ netdev_info(dev, "FPE: Respond mPacket is transmitted\n");
+ }
+
+ if (value & FPE_CTRL_STS_TVER) {
+ status |= FPE_EVENT_TVER;
+ netdev_info(dev, "FPE: Verify mPacket is transmitted\n");
+ }
+
+ if (value & FPE_CTRL_STS_RRSP) {
+ status |= FPE_EVENT_RRSP;
+ netdev_info(dev, "FPE: Respond mPacket is received\n");
+ }
+
+ if (value & FPE_CTRL_STS_RVER) {
+ status |= FPE_EVENT_RVER;
+ netdev_info(dev, "FPE: Verify mPacket is received\n");
+ }
+
+ return status;
+}
+
+static void __fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg,
+ enum stmmac_mpacket_type type)
+{
+ u32 value = cfg->fpe_csr;
+
+ if (type == MPACKET_VERIFY)
+ value |= FPE_CTRL_STS_SVER;
+ else if (type == MPACKET_RESPONSE)
+ value |= FPE_CTRL_STS_SRSP;
+
+ writel(value, ioaddr);
+}
+
+static void dwmac4_fpe_configure(void __iomem *ioaddr,
+ struct stmmac_fpe_cfg *cfg,
+ u32 num_txq, u32 num_rxq, bool enable)
+{
+ u32 value;
+
+ if (enable) {
+ cfg->fpe_csr = FPE_CTRL_STS_EFPE;
+ value = readl(ioaddr + GMAC_RXQ_CTRL1);
+ value &= ~GMAC_RXQCTRL_FPRQ;
+ value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;
+ writel(value, ioaddr + GMAC_RXQ_CTRL1);
+ } else {
+ cfg->fpe_csr = 0;
+ }
+
+ writel(cfg->fpe_csr, ioaddr + FPE_CTRL_STS_GMAC4_OFFSET);
+}
+
+static int dwmac4_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev)
+{
+ return __fpe_irq_status(ioaddr + FPE_CTRL_STS_GMAC4_OFFSET, dev);
+}
+
+static void dwmac4_fpe_send_mpacket(void __iomem *ioaddr,
+ struct stmmac_fpe_cfg *cfg,
+ enum stmmac_mpacket_type type)
+{
+ __fpe_send_mpacket(ioaddr + FPE_CTRL_STS_GMAC4_OFFSET, cfg, type);
+}
+
+const struct stmmac_fpe_ops dwmac4_fpe_ops = {
+ .configure = dwmac4_fpe_configure,
+ .irq_status = dwmac4_fpe_irq_status,
+ .send_mpacket = dwmac4_fpe_send_mpacket,
+};
@@ -4,6 +4,8 @@
* stmmac FPE(802.3 Qbu) handling
*/
+#define FPE_CTRL_STS_GMAC4_OFFSET 0x00000234
+
#define FPE_CTRL_STS_TRSP BIT(19)
#define FPE_CTRL_STS_TVER BIT(18)
#define FPE_CTRL_STS_RRSP BIT(17)
Introduce dwmac4_fpe_ops to complete the FPE implementation for DWMAC4 Signed-off-by: Furong Xu <0x1207@gmail.com> --- drivers/net/ethernet/stmicro/stmmac/hwif.c | 2 + drivers/net/ethernet/stmicro/stmmac/hwif.h | 1 + .../net/ethernet/stmicro/stmmac/stmmac_fpe.c | 85 +++++++++++++++++++ .../net/ethernet/stmicro/stmmac/stmmac_fpe.h | 2 + 4 files changed, 90 insertions(+)