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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 2/5] mlxsw: pci: Ring RDQ and CQ doorbells once per several completions Date: Fri, 26 Apr 2024 14:42:23 +0200 Message-ID: <82bebf03f3b33a50ea9f5a81048f29ddea5247af.1714134205.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F40:EE_|DM4PR12MB7624:EE_ X-MS-Office365-Filtering-Correlation-Id: a2269321-4c4b-445a-36f3-08dc65eeb46b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SHizurUsytgdYWZbhZj+VlqTT/EYNYuSeTjEP5D5fZue7DnbKu9abU+7zcNnJX5Z2IF1gkumYsBykyA+agU7x1L9GsidT2UM+7Di9Vmx0p2W55tVNyHs/D59gXkDjxkWEBbsWjpSa31wc8nkTn6dqGzlcPRFhL/83q8nvOAbVbgadjuEu8lZV2VYebGYWBWUhSQDCuxg8bRj67d1/W7RkspMIfUKLPURMNYjoQxN9Tgd5aQ/5AyCy7XnBAjHl9czOMsS3E/YnXbl0U6mIPp7kCu+OAy+f0Mck3jwM0aO7VyMg6wBtteOT2F2BDupMd1l0L4SjG3mPW3LIEF7Q5mB0gb6quqoU+3/xAfuEFOQKCOLFvxhOrW6CK54BPNlfutozVflW6WpDYmBIi2YA3xPpXP6wOun52O3xx5aw7ZYvp/P/6EIjacvmxbtrMskZLoAV/9fdBuFyjnDnS9UDed65c9FkzG7RZ0cuuyelbwXp4hqltZTy55fXsw7cROL8K/i/a2p2izKZAkbvrWOrcNBfQQvQthA1E3RJr48vEq9wX/A/X2leqxU+Pqb1SSKmiCNA7lxfZTk8a7lff7YVZEm1z66vQjo4VCxBEvsv2bnMVvvCOMcwQCNWVQ9nvR5Ztx/+UxH7ydoyAEefX6Mw98kysHd8dvADEPkGQrvWd5+vBqce3yWpkAwoeE4lHF72CdV9SYUVraI6+KHnN60ClFYMR1Xay+XU79mPB7XOjWVLRzGhvtQaV02P23iwGRPnCp5UfsY3J63C51OVwGSuGuCVfLwK3ePOcvEZBVqCrcGDp6IfHhle6o+1qnQSq7BfytzUwNQi2REYEZ5sinDExQi/Rro7tAHdpuTJgpLeYeXWZ0nCp/AlAv99prm2FLqGR54Fs/IofFc8fcEG3nQZ+Csi60j9JSsWs5qlqTfAdvdBdKfETFd3V2xOXjHkJ8RKI3R10LyRlCmF1DSeWRTrbMAaSq1P90rFOD66c6dFARFyqF2mRlQs8bJrcE5MCzpxonqgB6Y6tEC6ZzvjGgjS/TjgR2qYpOrYvpr0H9RIVQi7GcyxjJX8AMzJp7fdQsLgeOcEl9bA1jX1l0Z7uZk2bEerffPqGw4JGuPTQMbFwTSit3k+dxv4Rsc8PzlXTbW1whGYxWElVQA5st1qsQ0K5pgyHOCKdTH1g2R0NK/HntmnZULb2js64WASk0Th7yVVdJtzP4MFKd/Y1+yq1sG6mXTuxb7L/bhTPZRonn077RK27TCZ7HTbynBqtCoCn8g+S5Bf9GWbNF4Zp0W6jSGsnaQS2Q++A+MMB5LI3hFf07h499VSptORaTz9GdqgpY0MXoUW8dssRUPZ8NEqFLLEPBkUHCD+N/i1ixG0S4JCUcsN9v/9KoAewn4tBK0WIrKBETd X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230031)(376005)(1800799015)(82310400014)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Apr 2024 12:45:08.1908 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a2269321-4c4b-445a-36f3-08dc65eeb46b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F40.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7624 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen Currently, for each CQE in CQ, we ring CQ doorbell, then handle RDQ and ring RDQ doorbell. Finally we ring CQ arm doorbell - once per CQ tasklet. The idea of ringing CQ doorbell before RDQ doorbell, is to be sure that when we post new WQE (after RDQ is handled), there is an available CQE. This was done because of a hardware bug as part of commit c9ebea04cb1b ("mlxsw: pci: Ring CQ's doorbell before RDQ's"). There is no real reason to ring RDQ and CQ doorbells for each completion, it is better to handle several completions and reduce number of ringings, as access to hardware is expensive (time wise) and might take time because of memory barriers. A previous patch changed CQ tasklet to handle up to 64 Rx packets. With this limitation, we can ring CQ and RDQ doorbells once per CQ tasklet. The counters of the doorbells are increased by the amount of packets that we handled, then the device will know for which completion to send an additional event. To avoid reordering CQ and RDQ doorbells' ring, let the tasklet to ring also RDQ doorbell, mlxsw_pci_cqe_rdq_handle() handles the counter but does not ring the doorbell. Note that with this change there is no need to copy the CQE, as we ring CQ doorbell only after Rx packet processing (which uses the CQE) is done. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 8668947400ab..2094b802d8d5 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -630,9 +630,7 @@ static void mlxsw_pci_cqe_rdq_handle(struct mlxsw_pci *mlxsw_pci, mlxsw_core_skb_receive(mlxsw_pci->core, skb, &rx_info); out: - /* Everything is set up, ring doorbell to pass elem to HW */ q->producer_counter++; - mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, q); return; } @@ -666,7 +664,6 @@ static void mlxsw_pci_cq_rx_tasklet(struct tasklet_struct *t) u16 wqe_counter = mlxsw_pci_cqe_wqe_counter_get(cqe); u8 sendq = mlxsw_pci_cqe_sr_get(q->cq.v, cqe); u8 dqn = mlxsw_pci_cqe_dqn_get(q->cq.v, cqe); - char ncqe[MLXSW_PCI_CQE_SIZE_MAX]; if (unlikely(sendq)) { WARN_ON_ONCE(1); @@ -678,16 +675,15 @@ static void mlxsw_pci_cq_rx_tasklet(struct tasklet_struct *t) continue; } - memcpy(ncqe, cqe, q->elem_size); - mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); - mlxsw_pci_cqe_rdq_handle(mlxsw_pci, rdq, - wqe_counter, q->cq.v, ncqe); + wqe_counter, q->cq.v, cqe); if (++items == MLXSW_PCI_CQ_MAX_HANDLE) break; } + mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); + mlxsw_pci_queue_doorbell_producer_ring(mlxsw_pci, rdq); mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); }