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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Petr Machata , "Amit Cohen" , Subject: [PATCH net-next 1/7] mlxsw: pci: Split NAPI setup/teardown into two steps Date: Tue, 18 Jun 2024 13:34:40 +0200 Message-ID: <8dbf37e859f07247498fca17109b8858ff2b0498.1718709196.git.petrm@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|SA1PR12MB6869:EE_ X-MS-Office365-Filtering-Correlation-Id: a754d114-3361-4798-ec6e-08dc8f8ac40d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|1800799021|376011|36860700010|82310400023; X-Microsoft-Antispam-Message-Info: NWIZ29Lt6nDMpFsgi6cK49NT8dnzK1rUmi5LU8MYI1Z5hYVdAJHKc2d9VV5aL75Z1xuE7dk2WrjU+x+x/DMq28HdnbXO3Xyr84BL57u+PrF507NlbOaEk3wu3EKv77JBlvq1R/bDcFSVP0AZA4QWs2h47uclU8nhjC3zjawg/M5HEcCI9gxLKHfKBlJCR0nimtWt+hEqaRYB9j1EGkw4477O5axcfHZs5U1BH4iomrDcA8gbnlvP84s4jjD6I7bLBBQNt31m/2I1oRVbPpy3MuATBumvIhHtMP0SAgVizu8LKouKsduQQnVjNKwc9905zwwFPZEbCguDvUqWcFdiIDrEpWBtbpSMlMBYHqzgZwSrrGKsvhCoYbKB3CjvrHAugVs8TYIycQgAbKs5XeIQVfeXUo9Uon7R08IMKf5UQkmhSN9OmGYqNIH+iT3FZ+OuDIUdcrZEC3jEv1Dw1GjKK8iPneSUsffqgmsgq8N+NHKoPw1uSv/zKnUgycdq/oJSSfW0YzaSVFzT43eRxuvppW5FUhBMaoxXcld8e87UBB6rheCM6ZLiB3WJsBAuY+s6glm8hQjHV4/y6VO/+ayJlDKK/a7oid8BVN77/4fLQzZ8DwvswUh31Brzxn5UiFRwFK0vlsdw4e93lm3UHNmzj2nMV+QnPknApJPqmiOWLnGUsQMHPuM2IvPxFKsr+akz+Pe6F478w9+rHFfXldYP6/5e1AF263YfiX0oxRc9+2RV9xrYOLGywHjHfPzMcvSeY89MYMD7+TSNZjn6knXjJdeYTHMI2bwRrsd5QTsKq68DYK4ldC8kcCsDk/1NRpUEolOA9qqCV/F2/UngBk6rFVBNQksySmKm9DBBBq6qwdZkRKEnbLnAHnIoRpaqvSpxVqdphvcMTtpd+sjk3y+q6u9NFnurXpkAEvvdorej1WfayWjXXfSiOD4OCy0niouDlFBmv6u52WbK1dN/xcL+boh6B1euqBwUAdrHRjy2US4g5rEKx1Vq3TzH1n3O2t9bUZxxK6fs8Hji4/08brOXSBBY8RARxQVTl5ByT/LaXSXrAUngUcZevl6jFb61jfyt350HZSjBrEgnaMtLwdqw/Cq7CoMUcIjqSmHJf0ONS+b178pGYGMNRVua+rECkPdapghG7LTgwj75cFnR46L5sj+2nDQ6/H0BGuJJ2gA7k75r/MfXa3/jm5uVMaqx17xx0Yxj1aKbcAJxyX26T0HipH969R7Ww+JFSbP2xmLqnQwspEZGd13dZON5GVQZiJdtAm52RTs5EBk6nrykB/78K+iGozieoZY5pitzlqeyOKty10P2EUSO9TRoOOehWP/hNB14kJrqUTWfH/HttNpkhAful6fZN/mkZ+Yz7LP2MnUPtw+OM8+RpTC5AFAoLEjJF4kWK/lWN2HHfOJ8Da24eA== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230037)(1800799021)(376011)(36860700010)(82310400023);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2024 11:35:33.5242 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a754d114-3361-4798-ec6e-08dc8f8ac40d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6869 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen mlxsw_pci_cq_napi_setup() includes both NAPI initialization and enablement, similar to teardown function. Next patches will add support for page pool in mlxsw driver, then we use NAPI instance for page pool. Page pool initialization should be done before NAPI enablement, same for page pool destruction which should be done after NAPI disablement. As preparation, split NAPI setup/teardown into two steps, then page pool setup will be done between the phases. Signed-off-by: Amit Cohen Reviewed-by: Petr Machata Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index c0ced4d315f3..3b6afe3aa2a1 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -832,13 +832,10 @@ static void mlxsw_pci_cq_napi_setup(struct mlxsw_pci_queue *q, mlxsw_pci_napi_poll_cq_rx); break; } - - napi_enable(&q->u.cq.napi); } static void mlxsw_pci_cq_napi_teardown(struct mlxsw_pci_queue *q) { - napi_disable(&q->u.cq.napi); netif_napi_del(&q->u.cq.napi); } @@ -875,6 +872,7 @@ static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, if (err) return err; mlxsw_pci_cq_napi_setup(q, mlxsw_pci_cq_type(mlxsw_pci, q)); + napi_enable(&q->u.cq.napi); mlxsw_pci_queue_doorbell_consumer_ring(mlxsw_pci, q); mlxsw_pci_queue_doorbell_arm_consumer_ring(mlxsw_pci, q); return 0; @@ -883,6 +881,7 @@ static int mlxsw_pci_cq_init(struct mlxsw_pci *mlxsw_pci, char *mbox, static void mlxsw_pci_cq_fini(struct mlxsw_pci *mlxsw_pci, struct mlxsw_pci_queue *q) { + napi_disable(&q->u.cq.napi); mlxsw_pci_cq_napi_teardown(q); mlxsw_cmd_hw2sw_cq(mlxsw_pci->core, q->num); }