From patchwork Tue Oct 15 09:09:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Furong Xu <0x1207@gmail.com> X-Patchwork-Id: 13835964 X-Patchwork-Delegate: kuba@kernel.org Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 949E31DE2A9; Tue, 15 Oct 2024 09:10:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728983422; cv=none; b=sx0qQtUnWBl5RJXKk38yeWG4T6763+pdFV0OHDv/PD+UtG4wSeyBVQ2LotKbMASjUP+gltLZwHhMe1ua4UtufcH/4ZJgkT8HKrZ+a2dqbLHcqIFgneue2V8dq41Js8HfVW/jEm6E8TT3jfY4mB/QAy1+SVRlW3cHxJ71orsDhSU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728983422; c=relaxed/simple; bh=NsuHDFJ4dALYYYWC7bzTF2SzKeGQHQrboSrO8Lq4ZJE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rQT+sBVSt+9016tWn1qTuqT9hwwUOxzoT+FlnSORRLMH+QEzRYnrmX3vYFfwoRLTIcM7aISLQEdH8c/KhlyWSKPa1Xet5c78Lf6npnTZ/t1N3mZ8/aUv00LN0sGYqorHK7XqwViGwWOhkt80EAerCJ5YFrnRnd7CW9fb0cn+6Kk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=MwEqrlEq; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="MwEqrlEq" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-20cd76c513cso17857145ad.3; Tue, 15 Oct 2024 02:10:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1728983417; x=1729588217; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NWoScH18054s2usi/k8T15WQq1Q5xB2lrp04ckai9rc=; b=MwEqrlEqPb1WiuvNaoGWcgbTCyEw0q/RtqCO+5Tt4At/L80rzLC7LbV5+yTjTaoqwQ G1UIHoAnnbtzRC5lonFJy07z3zHiigtajI/I12XgewR1A+dq+DYImC71LQ8W3xO9/OFO E6U5O8PixPmOi51Cm3ZdqOnvRrmhLPjJCBnRmoE/ezxUlPmucUk35T5Rgw0c5kdHgUrI +ZKPVRP78tALeLZbbGRkm7NeFvY3pCHSWZOgZ2XBQ58EBKDH2yqBQQ/Q4HsjO6LGRi7l za/KWSmCg9TjOfEFOGvXBPKlbvecfQMDyHH8kxqX20eGmFBlNMYjz1GXLqs3nwX27+ga TaeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1728983417; x=1729588217; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NWoScH18054s2usi/k8T15WQq1Q5xB2lrp04ckai9rc=; b=wSMmr0223k0M2oQl/6R+8L9D/yg53Uf/S0X24z/5eJx9+e3ZRTZ/TUN1Pw7Oe9Z5q/ akLXcuCnndYyR3H6cbmAp4rZfink6Y89kwBgu0VZcScy5FPhNCXXBVD4z67bjPvf0C/L 3N2VGPv/k2F+2G4+Scw81KxbwrEWtnUzYi9dv4SCqD6D2gMbGJPJNAlKnz3A5KqsOTk+ QMY3Mt0JImPuKL4NM8oPZAelb/Zxn5xfSVClW2jud+hPf/4xvOfLo1Y4YzF2+cTbkyt2 FnW4cMwzz5F1aZItXXFNtU1aiY8KpFiHCPHpm7QjvIrD1dXjAVCI13I2Aaa1RyJFXXnZ XLRg== X-Forwarded-Encrypted: i=1; AJvYcCWRyAZ2cgYaX/QG6k9W71fKEkLAgyC832fmuggxsRU6TFLVfGzPx3VQLXeEuWs4EYYkhkOiQKBqjhc9GAc=@vger.kernel.org X-Gm-Message-State: AOJu0Yz+w8tIdeLdKsN/PTdiA5euQFCQSefAaHi4MbUP2bXN+7AOLcAc eew+LxXLJfdReCEP03TuALIMYZn2havAzTwqiFMhJmfqyjZlWGSmFJiyXw== X-Google-Smtp-Source: AGHT+IF7BjdMc88bz5iNPRCUEtA7OcOm4skitVJJp4ucxyRGNqFhnV2EscnqWOPOBDrDE+xz7S2jpA== X-Received: by 2002:a17:903:2309:b0:20b:8907:b597 with SMTP id d9443c01a7336-20ca1682ab9mr194221965ad.28.1728983417294; Tue, 15 Oct 2024 02:10:17 -0700 (PDT) Received: from localhost.localdomain ([129.146.253.192]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-20d17ec8f35sm7905095ad.0.2024.10.15.02.10.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2024 02:10:16 -0700 (PDT) From: Furong Xu <0x1207@gmail.com> To: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Vladimir Oltean , Andrew Lunn , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , xfr@outlook.com, Furong Xu <0x1207@gmail.com> Subject: [PATCH net-next v1 3/5] net: stmmac: Rework marco definitions for gmac4 and xgmac Date: Tue, 15 Oct 2024 17:09:24 +0800 Message-Id: <94705afa1d2815e82c27d3d1a13b2ad6ada8952f.1728980110.git.0x1207@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Rename and add marco definitions to better reuse them in common code. Signed-off-by: Furong Xu <0x1207@gmail.com> Reviewed-by: Simon Horman --- .../net/ethernet/stmicro/stmmac/stmmac_fpe.c | 49 ++++++++++--------- .../net/ethernet/stmicro/stmmac/stmmac_fpe.h | 26 +++++----- 2 files changed, 38 insertions(+), 37 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c index c01eb7243d56..0c13d5aee3d2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.c @@ -168,7 +168,7 @@ static void dwmac5_fpe_configure(void __iomem *ioaddr, u32 value; if (tx_enable) { - cfg->fpe_csr = EFPE; + cfg->fpe_csr = STMMAC_MAC_FPE_CTRL_STS_EFPE; value = readl(ioaddr + GMAC_RXQ_CTRL1); value &= ~GMAC_RXQCTRL_FPRQ; value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT; @@ -176,14 +176,14 @@ static void dwmac5_fpe_configure(void __iomem *ioaddr, } else { cfg->fpe_csr = 0; } - writel(cfg->fpe_csr, ioaddr + MAC_FPE_CTRL_STS); + writel(cfg->fpe_csr, ioaddr + GMAC5_MAC_FPE_CTRL_STS); value = readl(ioaddr + GMAC_INT_EN); if (pmac_enable) { if (!(value & GMAC_INT_FPE_EN)) { /* Dummy read to clear any pending masked interrupts */ - readl(ioaddr + MAC_FPE_CTRL_STS); + readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS); value |= GMAC_INT_FPE_EN; } @@ -204,24 +204,24 @@ static int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) /* Reads from the MAC_FPE_CTRL_STS register should only be performed * here, since the status flags of MAC_FPE_CTRL_STS are "clear on read" */ - value = readl(ioaddr + MAC_FPE_CTRL_STS); + value = readl(ioaddr + GMAC5_MAC_FPE_CTRL_STS); - if (value & TRSP) { + if (value & STMMAC_MAC_FPE_CTRL_STS_TRSP) { status |= FPE_EVENT_TRSP; netdev_dbg(dev, "FPE: Respond mPacket is transmitted\n"); } - if (value & TVER) { + if (value & STMMAC_MAC_FPE_CTRL_STS_TVER) { status |= FPE_EVENT_TVER; netdev_dbg(dev, "FPE: Verify mPacket is transmitted\n"); } - if (value & RRSP) { + if (value & STMMAC_MAC_FPE_CTRL_STS_RRSP) { status |= FPE_EVENT_RRSP; netdev_dbg(dev, "FPE: Respond mPacket is received\n"); } - if (value & RVER) { + if (value & STMMAC_MAC_FPE_CTRL_STS_RVER) { status |= FPE_EVENT_RVER; netdev_dbg(dev, "FPE: Verify mPacket is received\n"); } @@ -236,16 +236,17 @@ static void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, u32 value = cfg->fpe_csr; if (type == MPACKET_VERIFY) - value |= SVER; + value |= STMMAC_MAC_FPE_CTRL_STS_SVER; else if (type == MPACKET_RESPONSE) - value |= SRSP; + value |= STMMAC_MAC_FPE_CTRL_STS_SRSP; - writel(value, ioaddr + MAC_FPE_CTRL_STS); + writel(value, ioaddr + GMAC5_MAC_FPE_CTRL_STS); } static int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr) { - return FIELD_GET(DWMAC5_ADD_FRAG_SZ, readl(ioaddr + MTL_FPE_CTRL_STS)); + return FIELD_GET(FPE_MTL_ADD_FRAG_SZ, + readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS)); } static void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, @@ -253,9 +254,9 @@ static void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, { u32 value; - value = readl(ioaddr + MTL_FPE_CTRL_STS); - writel(u32_replace_bits(value, add_frag_size, DWMAC5_ADD_FRAG_SZ), - ioaddr + MTL_FPE_CTRL_STS); + value = readl(ioaddr + GMAC5_MTL_FPE_CTRL_STS); + writel(u32_replace_bits(value, add_frag_size, FPE_MTL_ADD_FRAG_SZ), + ioaddr + GMAC5_MTL_FPE_CTRL_STS); } #define ALG_ERR_MSG "TX algorithm SP is not suitable for one-to-many mapping" @@ -307,9 +308,9 @@ static int dwmac5_fpe_map_preemption_class(struct net_device *ndev, } update_mapping: - val = readl(priv->ioaddr + MTL_FPE_CTRL_STS); - writel(u32_replace_bits(val, preemptible_txqs, DWMAC5_PREEMPTION_CLASS), - priv->ioaddr + MTL_FPE_CTRL_STS); + val = readl(priv->ioaddr + GMAC5_MTL_FPE_CTRL_STS); + writel(u32_replace_bits(val, preemptible_txqs, FPE_MTL_PREEMPTION_CLASS), + priv->ioaddr + GMAC5_MTL_FPE_CTRL_STS); return 0; } @@ -322,11 +323,11 @@ static void dwxgmac3_fpe_configure(void __iomem *ioaddr, u32 value; if (!tx_enable) { - value = readl(ioaddr + XGMAC_FPE_CTRL_STS); + value = readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS); - value &= ~XGMAC_EFPE; + value &= ~STMMAC_MAC_FPE_CTRL_STS_EFPE; - writel(value, ioaddr + XGMAC_FPE_CTRL_STS); + writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS); return; } @@ -335,9 +336,9 @@ static void dwxgmac3_fpe_configure(void __iomem *ioaddr, value |= (num_rxq - 1) << XGMAC_RQ_SHIFT; writel(value, ioaddr + XGMAC_RXQ_CTRL1); - value = readl(ioaddr + XGMAC_FPE_CTRL_STS); - value |= XGMAC_EFPE; - writel(value, ioaddr + XGMAC_FPE_CTRL_STS); + value = readl(ioaddr + XGMAC_MAC_FPE_CTRL_STS); + value |= STMMAC_MAC_FPE_CTRL_STS_EFPE; + writel(value, ioaddr + XGMAC_MAC_FPE_CTRL_STS); } const struct stmmac_fpe_ops dwmac5_fpe_ops = { diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h index a113b5c57de9..c0305f11575b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_fpe.h @@ -8,23 +8,23 @@ #define STMMAC_FPE_MM_MAX_VERIFY_RETRIES 3 #define STMMAC_FPE_MM_MAX_VERIFY_TIME_MS 128 -#define MAC_FPE_CTRL_STS 0x00000234 -#define TRSP BIT(19) -#define TVER BIT(18) -#define RRSP BIT(17) -#define RVER BIT(16) -#define SRSP BIT(2) -#define SVER BIT(1) -#define EFPE BIT(0) +#define GMAC5_MAC_FPE_CTRL_STS 0x00000234 +#define XGMAC_MAC_FPE_CTRL_STS 0x00000280 -#define MTL_FPE_CTRL_STS 0x00000c90 +#define GMAC5_MTL_FPE_CTRL_STS 0x00000c90 +#define XGMAC_MTL_FPE_CTRL_STS 0x00001090 /* Preemption Classification */ -#define DWMAC5_PREEMPTION_CLASS GENMASK(15, 8) +#define FPE_MTL_PREEMPTION_CLASS GENMASK(15, 8) /* Additional Fragment Size of preempted frames */ -#define DWMAC5_ADD_FRAG_SZ GENMASK(1, 0) +#define FPE_MTL_ADD_FRAG_SZ GENMASK(1, 0) -#define XGMAC_FPE_CTRL_STS 0x00000280 -#define XGMAC_EFPE BIT(0) +#define STMMAC_MAC_FPE_CTRL_STS_TRSP BIT(19) +#define STMMAC_MAC_FPE_CTRL_STS_TVER BIT(18) +#define STMMAC_MAC_FPE_CTRL_STS_RRSP BIT(17) +#define STMMAC_MAC_FPE_CTRL_STS_RVER BIT(16) +#define STMMAC_MAC_FPE_CTRL_STS_SRSP BIT(2) +#define STMMAC_MAC_FPE_CTRL_STS_SVER BIT(1) +#define STMMAC_MAC_FPE_CTRL_STS_EFPE BIT(0) /* FPE link-partner hand-shaking mPacket type */ enum stmmac_mpacket_type {