diff mbox series

[1/1] clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL

Message ID AS1P250MB0608F9CE4009DCE65C61EEDEA9922@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM (mailing list archive)
State Not Applicable
Headers show
Series [1/1] clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL | expand

Checks

Context Check Description
netdev/tree_selection success Not a local patch

Commit Message

Michel Alex Sept. 2, 2024, 9:05 a.m. UTC 
Commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ("clk: imx6ul: add
ethernet refclock mux support") sets the internal clock as default
ethernet clock.

Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL,
the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct
parent and shall be used instead.
Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M
is the correct parent.

Cc: stable@vger.kernel.org
Signed-off-by: Alex Michel <alex.michel@wiedemann-group.com>
---
 drivers/clk/imx/clk-imx6ul.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Abel Vesa Sept. 4, 2024, 9:43 a.m. UTC | #1 
On Mon, 02 Sep 2024 09:05:53 +0000, Michel Alex wrote:
> Commit 4e197ee880c24ecb63f7fe17449b3653bc64b03c ("clk: imx6ul: add
> ethernet refclock mux support") sets the internal clock as default
> ethernet clock.
> 
> Since IMX6UL_CLK_ENET_REF cannot be parent for IMX6UL_CLK_ENET1_REF_SEL,
> the call to clk_set_parent() fails. IMX6UL_CLK_ENET1_REF_125M is the correct
> parent and shall be used instead.
> Same applies for IMX6UL_CLK_ENET2_REF_SEL, for which IMX6UL_CLK_ENET2_REF_125M
> is the correct parent.
> 
> [...]

Applied, thanks!

[1/1] clk: imx6ul: fix clock parent for IMX6UL_CLK_ENETx_REF_SEL
      commit: 32c055ef563c3a4a73a477839f591b1b170bde8e

Best regards,
diff mbox series

Patch

diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index f9394e94f69d..05c7a82b751f 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -542,8 +542,8 @@  static void __init imx6ul_clocks_init(struct device_node *ccm_node)
 
 	clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk);
 
-	clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET_REF]->clk);
-	clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF]->clk);
+	clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET1_REF_125M]->clk);
+	clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF_125M]->clk);
 
 	imx_register_uart_clocks();
 }