@@ -706,7 +706,8 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
break;
}
- if (xpcs->sgmii_mode == DW_XPCS_SGMII_MODE_MAC)
+ if (xpcs->sgmii_mode == DW_XPCS_SGMII_MODE_MAC_AUTO ||
+ xpcs->sgmii_mode == DW_XPCS_SGMII_MODE_MAC_MANUAL)
tx_conf = DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII;
else
tx_conf = DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII;
@@ -721,11 +722,14 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs,
mask = DW_VR_MII_DIG_CTRL1_2G5_EN | DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
switch (xpcs->sgmii_mode) {
- case DW_XPCS_SGMII_MODE_MAC:
+ case DW_XPCS_SGMII_MODE_MAC_AUTO:
if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
val = DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
break;
+ case DW_XPCS_SGMII_MODE_MAC_MANUAL:
+ break;
+
case DW_XPCS_SGMII_MODE_PHY_HW:
mask |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL;
val |= DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL;
@@ -1151,7 +1155,9 @@ static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs,
{
int ret;
- if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED &&
+ !(interface == PHY_INTERFACE_MODE_SGMII &&
+ xpcs->sgmii_mode == DW_XPCS_SGMII_MODE_MAC_MANUAL))
return;
if (interface == PHY_INTERFACE_MODE_1000BASEX) {
@@ -1168,10 +1174,11 @@ static void xpcs_link_up_sgmii_1000basex(struct dw_xpcs *xpcs,
__func__);
}
- ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MII_BMCR,
- mii_bmcr_encode_fixed(speed, duplex));
+ ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, MII_BMCR,
+ BMCR_SPEED1000 | BMCR_FULLDPLX | BMCR_SPEED100,
+ mii_bmcr_encode_fixed(speed, duplex));
if (ret)
- dev_err(&xpcs->mdiodev->dev, "%s: xpcs_write returned %pe\n",
+ dev_err(&xpcs->mdiodev->dev, "%s: xpcs_modify returned %pe\n",
__func__, ERR_PTR(ret));
}
@@ -121,15 +121,20 @@ enum dw_xpcs_sgmii_10_100 {
};
/* The SGMII mode:
- * DW_XPCS_SGMII_MODE_MAC: the XPCS acts as a MAC, reading and acknowledging
- * the config word.
+ * DW_XPCS_SGMII_MODE_MAC_AUTO: the XPCS acts as a MAC, accepting the
+ * parameters from the PHY end of the SGMII link and acknowledging the
+ * config word. The XPCS autonomously switches speed.
+ *
+ * DW_XPCS_SGMII_MODE_MAC_MANUAL: the XPCS acts as a MAC as above, but
+ * does not autonomously switch speed.
*
* DW_XPCS_SGMII_MODE_PHY_HW: the XPCS acts as a PHY, deriving the tx_config
* bits 15 (link), 12 (duplex) and 11:10 (speed) from hardware inputs to the
* XPCS.
*/
enum dw_xpcs_sgmii_mode {
- DW_XPCS_SGMII_MODE_MAC, /* XPCS is MAC on SGMII */
+ DW_XPCS_SGMII_MODE_MAC_AUTO, /* XPCS is MAC, auto update */
+ DW_XPCS_SGMII_MODE_MAC_MANUAL, /* XPCS is MAC, manual update */
DW_XPCS_SGMII_MODE_PHY_HW, /* XPCS is PHY, tx_config from hw */
};
Older revisions of the XPCS IP do not support the MAC_AUTO_SW flag and need the BMCR register updated with the speed information from the PHY. Split the DW_XPCS_SGMII_MODE_MAC mode into _AUTO and _MANUAL variants, where _AUTO mode means the update happens in hardware autonomously, whereas the _MANUAL mode means that we need to update the BMCR register when the link comes up. This will be required for the older XPCS IP found in KSZ9477. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> --- This needs further input from Tristram Ha / Microchip to work out a way to detect KSZ9477 and set DW_XPCS_SGMII_MODE_MAC_MANUAL. On its own, this patch does nothing. --- drivers/net/pcs/pcs-xpcs.c | 19 +++++++++++++------ drivers/net/pcs/pcs-xpcs.h | 11 ++++++++--- 2 files changed, 21 insertions(+), 9 deletions(-)