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Wed, 1 May 2024 16:03:49 +0000 From: Min Li To: richardcochran@gmail.com, lee@kernel.org Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Min Li Subject: [PATCH net-next v7 2/5] ptp: clockmatrix: set write phase timer to 0 when not in PCW mode Date: Wed, 1 May 2024 12:03:21 -0400 Message-ID: X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240501160324.27514-1-lnimi@hotmail.com> References: <20240501160324.27514-1-lnimi@hotmail.com> X-TMN: [s8DxCGAQNMLbDw9DM+3qodYaozPpWVtu] X-ClientProxiedBy: MN2PR18CA0016.namprd18.prod.outlook.com (2603:10b6:208:23c::21) To LV3P220MB1202.NAMP220.PROD.OUTLOOK.COM (2603:10b6:408:1ac::6) X-Microsoft-Original-Message-ID: <20240501160324.27514-3-lnimi@hotmail.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV3P220MB1202:EE_|EA2P220MB1331:EE_ X-MS-Office365-Filtering-Correlation-Id: 77b13769-f676-4591-5506-08dc69f84914 X-Microsoft-Antispam: BCL:0;ARA:14566002|461199019|440099019|3412199016; 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Also Fix u8 -> u16, DPLL_WF_TIMER and DPLL_WP_TIMER are 2-byte registers Signed-off-by: Min Li --- drivers/ptp/ptp_clockmatrix.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c index f8556627befa..d069b6e451ef 100644 --- a/drivers/ptp/ptp_clockmatrix.c +++ b/drivers/ptp/ptp_clockmatrix.c @@ -1396,6 +1396,20 @@ static int idtcm_set_pll_mode(struct idtcm_channel *channel, struct idtcm *idtcm = channel->idtcm; int err; u8 dpll_mode; + u8 buf[2] = {0}; + + /* Setup WF/WP timer for phase pull-in to work correctly */ + err = idtcm_write(idtcm, channel->dpll_n, DPLL_WF_TIMER, + buf, sizeof(buf)); + if (err) + return err; + + if (mode == PLL_MODE_WRITE_PHASE) + buf[0] = 160; + err = idtcm_write(idtcm, channel->dpll_n, DPLL_WP_TIMER, + buf, sizeof(buf)); + if (err) + return err; err = idtcm_read(idtcm, channel->dpll_n, IDTCM_FW_REG(idtcm->fw_ver, V520, DPLL_MODE),