diff --git a/drivers/net/phy/dp83tg720.c b/drivers/net/phy/dp83tg720.c
index 0ef4d7dba065..7e81800cfc5b 100644
--- a/drivers/net/phy/dp83tg720.c
+++ b/drivers/net/phy/dp83tg720.c
@@ -10,62 +10,62 @@
 
 #include "open_alliance_helpers.h"
 
-#define DP83TG720S_PHY_ID			0x2000a284
+#define DP83TG720_PHY_ID			0x2000a284
 
 /* MDIO_MMD_VEND2 registers */
-#define DP83TG720S_MII_REG_10			0x10
-#define DP83TG720S_STS_MII_INT			BIT(7)
-#define DP83TG720S_LINK_STATUS			BIT(0)
+#define DP83TG720_MII_REG_10			0x10
+#define DP83TG720_STS_MII_INT			BIT(7)
+#define DP83TG720_LINK_STATUS			BIT(0)
 
 /* TDR Configuration Register (0x1E) */
-#define DP83TG720S_TDR_CFG			0x1e
+#define DP83TG720_TDR_CFG			0x1e
 /* 1b = TDR start, 0b = No TDR */
-#define DP83TG720S_TDR_START			BIT(15)
+#define DP83TG720_TDR_START			BIT(15)
 /* 1b = TDR auto on link down, 0b = Manual TDR start */
-#define DP83TG720S_CFG_TDR_AUTO_RUN		BIT(14)
+#define DP83TG720_CFG_TDR_AUTO_RUN		BIT(14)
 /* 1b = TDR done, 0b = TDR in progress */
-#define DP83TG720S_TDR_DONE			BIT(1)
+#define DP83TG720_TDR_DONE			BIT(1)
 /* 1b = TDR fail, 0b = TDR success */
-#define DP83TG720S_TDR_FAIL			BIT(0)
+#define DP83TG720_TDR_FAIL			BIT(0)
 
-#define DP83TG720S_PHY_RESET			0x1f
-#define DP83TG720S_HW_RESET			BIT(15)
+#define DP83TG720_PHY_RESET			0x1f
+#define DP83TG720_HW_RESET			BIT(15)
 
-#define DP83TG720S_LPS_CFG3			0x18c
+#define DP83TG720_LPS_CFG3			0x18c
 /* Power modes are documented as bit fields but used as values */
 /* Power Mode 0 is Normal mode */
-#define DP83TG720S_LPS_CFG3_PWR_MODE_0		BIT(0)
+#define DP83TG720_LPS_CFG3_PWR_MODE_0		BIT(0)
 
 /* Open Aliance 1000BaseT1 compatible HDD.TDR Fault Status Register */
-#define DP83TG720S_TDR_FAULT_STATUS		0x30f
+#define DP83TG720_TDR_FAULT_STATUS		0x30f
 
 /* Register 0x0301: TDR Configuration 2 */
-#define DP83TG720S_TDR_CFG2			0x301
+#define DP83TG720_TDR_CFG2			0x301
 
 /* Register 0x0303: TDR Configuration 3 */
-#define DP83TG720S_TDR_CFG3			0x303
+#define DP83TG720_TDR_CFG3			0x303
 
 /* Register 0x0304: TDR Configuration 4 */
-#define DP83TG720S_TDR_CFG4			0x304
+#define DP83TG720_TDR_CFG4			0x304
 
 /* Register 0x0405: Unknown Register */
-#define DP83TG720S_UNKNOWN_0405			0x405
+#define DP83TG720_UNKNOWN_0405			0x405
 
 /* Register 0x0576: TDR Master Link Down Control */
-#define DP83TG720S_TDR_MASTER_LINK_DOWN		0x576
+#define DP83TG720_TDR_MASTER_LINK_DOWN		0x576
 
-#define DP83TG720S_RGMII_DELAY_CTRL		0x602
+#define DP83TG720_RGMII_DELAY_CTRL		0x602
 /* In RGMII mode, Enable or disable the internal delay for RXD */
-#define DP83TG720S_RGMII_RX_CLK_SEL		BIT(1)
+#define DP83TG720_RGMII_RX_CLK_SEL		BIT(1)
 /* In RGMII mode, Enable or disable the internal delay for TXD */
-#define DP83TG720S_RGMII_TX_CLK_SEL		BIT(0)
+#define DP83TG720_RGMII_TX_CLK_SEL		BIT(0)
 
 /* Register 0x083F: Unknown Register */
-#define DP83TG720S_UNKNOWN_083F			0x83f
+#define DP83TG720_UNKNOWN_083F			0x83f
 
-#define DP83TG720S_SQI_REG_1			0x871
-#define DP83TG720S_SQI_OUT_WORST		GENMASK(7, 5)
-#define DP83TG720S_SQI_OUT			GENMASK(3, 1)
+#define DP83TG720_SQI_REG_1			0x871
+#define DP83TG720_SQI_OUT_WORST		GENMASK(7, 5)
+#define DP83TG720_SQI_OUT			GENMASK(3, 1)
 
 #define DP83TG720_SQI_MAX			7
 
@@ -82,7 +82,7 @@ static int dp83tg720_cable_test_start(struct phy_device *phydev)
 	int ret;
 
 	/* Initialize the PHY to run the TDR test as described in the
-	 * "DP83TG720S-Q1: Configuring for Open Alliance Specification
+	 * "DP83TG720-Q1: Configuring for Open Alliance Specification
 	 * Compliance (Rev. B)" application note.
 	 * Most of the registers are not documented. Some of register names
 	 * are guessed by comparing the register offsets with the DP83TD510E.
@@ -90,38 +90,38 @@ static int dp83tg720_cable_test_start(struct phy_device *phydev)
 
 	/* Force master link down */
 	ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
-			       DP83TG720S_TDR_MASTER_LINK_DOWN, 0x0400);
+			       DP83TG720_TDR_MASTER_LINK_DOWN, 0x0400);
 	if (ret)
 		return ret;
 
-	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG2,
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_TDR_CFG2,
 			    0xa008);
 	if (ret)
 		return ret;
 
-	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG3,
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_TDR_CFG3,
 			    0x0928);
 	if (ret)
 		return ret;
 
-	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG4,
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_TDR_CFG4,
 			    0x0004);
 	if (ret)
 		return ret;
 
-	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_0405,
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_UNKNOWN_0405,
 			    0x6400);
 	if (ret)
 		return ret;
 
-	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_083F,
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_UNKNOWN_083F,
 			    0x3003);
 	if (ret)
 		return ret;
 
 	/* Start the TDR */
-	ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG,
-			       DP83TG720S_TDR_START);
+	ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_TDR_CFG,
+			       DP83TG720_TDR_START);
 	if (ret)
 		return ret;
 
@@ -146,21 +146,21 @@ static int dp83tg720_cable_test_get_status(struct phy_device *phydev,
 	*finished = false;
 
 	/* Read the TDR status */
-	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG);
+	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_TDR_CFG);
 	if (ret < 0)
 		return ret;
 
 	/* Check if the TDR test is done */
-	if (!(ret & DP83TG720S_TDR_DONE))
+	if (!(ret & DP83TG720_TDR_DONE))
 		return 0;
 
 	/* Check for TDR test failure */
-	if (!(ret & DP83TG720S_TDR_FAIL)) {
+	if (!(ret & DP83TG720_TDR_FAIL)) {
 		int location;
 
 		/* Read fault status */
 		ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
-				   DP83TG720S_TDR_FAULT_STATUS);
+				   DP83TG720_TDR_FAULT_STATUS);
 		if (ret < 0)
 			return ret;
 
@@ -214,8 +214,8 @@ static int dp83tg720_read_status(struct phy_device *phydev)
 	/* Most of Clause 45 registers are not present, so we can't use
 	 * genphy_c45_read_status() here.
 	 */
-	phy_sts = phy_read(phydev, DP83TG720S_MII_REG_10);
-	phydev->link = !!(phy_sts & DP83TG720S_LINK_STATUS);
+	phy_sts = phy_read(phydev, DP83TG720_MII_REG_10);
+	phydev->link = !!(phy_sts & DP83TG720_LINK_STATUS);
 	if (!phydev->link) {
 		/* According to the "DP83TC81x, DP83TG72x Software
 		 * Implementation Guide", the PHY needs to be reset after a
@@ -261,11 +261,11 @@ static int dp83tg720_get_sqi(struct phy_device *phydev)
 	if (!phydev->link)
 		return 0;
 
-	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_SQI_REG_1);
+	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_SQI_REG_1);
 	if (ret < 0)
 		return ret;
 
-	return FIELD_GET(DP83TG720S_SQI_OUT, ret);
+	return FIELD_GET(DP83TG720_SQI_OUT, ret);
 }
 
 static int dp83tg720_get_sqi_max(struct phy_device *phydev)
@@ -283,24 +283,24 @@ static int dp83tg720_config_rgmii_delay(struct phy_device *phydev)
 		rgmii_delay = 0;
 		break;
 	case PHY_INTERFACE_MODE_RGMII_ID:
-		rgmii_delay = DP83TG720S_RGMII_RX_CLK_SEL |
-				DP83TG720S_RGMII_TX_CLK_SEL;
+		rgmii_delay = DP83TG720_RGMII_RX_CLK_SEL |
+				DP83TG720_RGMII_TX_CLK_SEL;
 		break;
 	case PHY_INTERFACE_MODE_RGMII_RXID:
-		rgmii_delay = DP83TG720S_RGMII_RX_CLK_SEL;
+		rgmii_delay = DP83TG720_RGMII_RX_CLK_SEL;
 		break;
 	case PHY_INTERFACE_MODE_RGMII_TXID:
-		rgmii_delay = DP83TG720S_RGMII_TX_CLK_SEL;
+		rgmii_delay = DP83TG720_RGMII_TX_CLK_SEL;
 		break;
 	default:
 		return 0;
 	}
 
-	rgmii_delay_mask = DP83TG720S_RGMII_RX_CLK_SEL |
-		DP83TG720S_RGMII_TX_CLK_SEL;
+	rgmii_delay_mask = DP83TG720_RGMII_RX_CLK_SEL |
+		DP83TG720_RGMII_TX_CLK_SEL;
 
 	return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
-			      DP83TG720S_RGMII_DELAY_CTRL, rgmii_delay_mask,
+			      DP83TG720_RGMII_DELAY_CTRL, rgmii_delay_mask,
 			      rgmii_delay);
 }
 
@@ -311,12 +311,12 @@ static int dp83tg720_config_init(struct phy_device *phydev)
 	/* Software Restart is not enough to recover from a link failure.
 	 * Using Hardware Reset instead.
 	 */
-	ret = phy_write(phydev, DP83TG720S_PHY_RESET, DP83TG720S_HW_RESET);
+	ret = phy_write(phydev, DP83TG720_PHY_RESET, DP83TG720_HW_RESET);
 	if (ret)
 		return ret;
 
 	/* Wait until MDC can be used again.
-	 * The wait value of one 1ms is documented in "DP83TG720S-Q1 1000BASE-T1
+	 * The wait value of one 1ms is documented in "DP83TG720-Q1 1000BASE-T1
 	 * Automotive Ethernet PHY with SGMII and RGMII" datasheet.
 	 */
 	usleep_range(1000, 2000);
@@ -330,8 +330,8 @@ static int dp83tg720_config_init(struct phy_device *phydev)
 	/* In case the PHY is bootstrapped in managed mode, we need to
 	 * wake it.
 	 */
-	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_LPS_CFG3,
-			    DP83TG720S_LPS_CFG3_PWR_MODE_0);
+	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720_LPS_CFG3,
+			    DP83TG720_LPS_CFG3_PWR_MODE_0);
 	if (ret)
 		return ret;
 
@@ -343,8 +343,8 @@ static int dp83tg720_config_init(struct phy_device *phydev)
 
 static struct phy_driver dp83tg720_driver[] = {
 {
-	PHY_ID_MATCH_MODEL(DP83TG720S_PHY_ID),
-	.name		= "TI DP83TG720S",
+	PHY_ID_MATCH_MODEL(DP83TG720_PHY_ID),
+	.name		= "TI DP83TG720",
 
 	.flags          = PHY_POLL_CABLE_TEST,
 	.config_aneg	= dp83tg720_config_aneg,
@@ -362,11 +362,11 @@ static struct phy_driver dp83tg720_driver[] = {
 module_phy_driver(dp83tg720_driver);
 
 static struct mdio_device_id __maybe_unused dp83tg720_tbl[] = {
-	{ PHY_ID_MATCH_MODEL(DP83TG720S_PHY_ID) },
+	{ PHY_ID_MATCH_MODEL(DP83TG720_PHY_ID) },
 	{ }
 };
 MODULE_DEVICE_TABLE(mdio, dp83tg720_tbl);
 
-MODULE_DESCRIPTION("Texas Instruments DP83TG720S PHY driver");
+MODULE_DESCRIPTION("Texas Instruments DP83TG720 PHY driver");
 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
 MODULE_LICENSE("GPL");
