From patchwork Fri Feb 7 02:06:00 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peilin Ye X-Patchwork-Id: 13964226 X-Patchwork-Delegate: bpf@iogearbox.net Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00D311487C8 for ; Fri, 7 Feb 2025 02:06:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738893969; cv=none; b=mRJqlTpLG6MQ3pK4vKHfiDZOJEvCH6rOOGnAuh2TmXXh+o4Om1eB+/CCSGjsVvSCQdHhZZVYngMK1yUn+eoc+THw9c9yYzQBlSy4pVyytAdEeIEeeR2Ym7y94aopix014ESMfWvpUkP+vs3k0Kex0d0b7nO/WmMQN+dy/7TK9bg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738893969; c=relaxed/simple; bh=E/TpMA247bMkzLdjcLrFOFBXXFCSKNXD47s95nK47Vs=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=neNfjLrOY/KUj9OA1DiITOFQCDewKbtheWiYMkdSzRJH7HxB1uIkke2+xrAV6jCd2zCAIu5H5t9Vn6D8SAhzn6Uajy1HgxDNFRmczVAAVpvCOxYqtbKF15upSmz3ilJmi+0/BVtch9bVHs7vKE5m4mGiFTeqTLJIK9DWuo/vLcg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--yepeilin.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=UXUnvLq6; arc=none smtp.client-ip=209.85.216.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--yepeilin.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="UXUnvLq6" Received: by mail-pj1-f73.google.com with SMTP id 98e67ed59e1d1-2fa1e63a5ffso2428870a91.3 for ; Thu, 06 Feb 2025 18:06:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1738893967; x=1739498767; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=yopLqhfx9FBzsjoQTq5VQnotD7AE589toKqt2dLQW/g=; b=UXUnvLq6tWkJmLQUeX7EbyTEIYhXmvz7FLItJRJExYkvD7xrzAdz+0P4RGGvOdRU2L LVlu0O/Jy2zhChNQ2+QdX65Lzg5fZ98Wn5AW8AO+tD0uVCWwxlcHG6fULpPXGjbdbMgk z3629GSiL3wey7GKeb4bpbjqM2dlsaVUG+BV5U9cJ6Lqw4fQmkHzBBIaEbjHaIAcAYyC oEohSuvFd2swVQhYyv2yziKt7PbamQBoVJGLYhXpyUsCAzJ0+nj7Ier3ovaS/KchzSJ+ yYCW9C1MU5e2xW16yNkeBgtlDxnoyBdBuDnfJbCEChMJ0q/Y9X8bZolzR35UadK2SQwA wx/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738893967; x=1739498767; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=yopLqhfx9FBzsjoQTq5VQnotD7AE589toKqt2dLQW/g=; b=eMMDBLaHafh4AGlwqx95sWR+HC1Q9EOZ9E3s6ywx8Mo0TZ2OQdyGBP2+EdjzrTeqZ0 H/2D8zc7L/qOBQfRE9jKiFcE3u+VSTZKMKIith2bx6aKune3ygauI3VCyIsxeT2Db8bY Kmgh+7th8Db0H91gdO+dycBYPK0YmX6AIqzPkwn9S2Ojsmqp3CYKBov1iUFyjwXC+oqh bXRncmo73mQ7XaqD2YmnJs327zMWnX+gtHIqAwUnBWxMjqf+wb+hnWSeOUEYYkAqwpQZ 1DqiPlo/Bw2NygwLyb9L27uop95dXMDMZP7UrwKtbIbzatX9rKLVu6/YhcCOaGRDg4sF YsKQ== X-Gm-Message-State: AOJu0Yz0LgJNOZYjhQXeuGVz6fo3AzLmT+6ygakk47kRKRr/9k7c3UOc BZ6cK5Q/ckC52I1hsqbqstWs1Hhm+qzISS5wEdKers6fPOfso/uJ6JLjfKNaOOVNP93KANhfmCe pxH/rlKqIfiVjlva5Ncb39L6jToT4SkGucSqhKJhoJC4PZm9YGRR4oZD9v9fX4054aK9fO1BTsf Z6RuwQtetrQrvVdCVd+uXel3zIqNTxVE07bRd0IsE= X-Google-Smtp-Source: AGHT+IFkXM4xOo99sOcxT31u2xnrLGGSfuSlHl8QgKpY5jPoM6In+piNqVi02IXVxH8TVZTEDBs9f2fc1XsrBg== X-Received: from pjbpt7.prod.google.com ([2002:a17:90b:3d07:b0:2fa:b84:b308]) (user=yepeilin job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:3dc3:b0:2ee:8ea0:6b9c with SMTP id 98e67ed59e1d1-2fa24064223mr2524108a91.12.1738893966755; Thu, 06 Feb 2025 18:06:06 -0800 (PST) Date: Fri, 7 Feb 2025 02:06:00 +0000 In-Reply-To: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: X-Mailer: git-send-email 2.48.1.502.g6dc24dfdaf-goog Message-ID: Subject: [PATCH bpf-next v2 5/9] arm64: insn: Add BIT(23) to {load,store}_ex's mask From: Peilin Ye To: bpf@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Peilin Ye , bpf@ietf.org, Xu Kuohai , Eduard Zingerman , David Vernet , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Jonathan Corbet , "Paul E. McKenney" , Puranjay Mohan , Ilya Leoshkevich , Heiko Carstens , Vasily Gorbik , Catalin Marinas , Will Deacon , Quentin Monnet , Mykola Lysenko , Shuah Khan , Ihor Solodrai , Yingchi Long , Josh Don , Barret Rhoden , Neel Natu , Benjamin Segall , linux-kernel@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net We are planning to add load-acquire (LDAR{,B,H}) and store-release (STLR{,B,H}) instructions to insn.{c,h}; add BIT(23) to mask of load_ex and store_ex to prevent aarch64_insn_is_{load,store}_ex() from returning false-positives for load-acquire and store-release instructions. Reference: Arm Architecture Reference Manual (ARM DDI 0487K.a, ID032224), * C6.2.228 LDXR * C6.2.165 LDAXR * C6.2.161 LDAR * C6.2.393 STXR * C6.2.360 STLXR * C6.2.353 STLR Signed-off-by: Peilin Ye --- arch/arm64/include/asm/insn.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index e390c432f546..2d8316b3abaf 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -351,8 +351,8 @@ __AARCH64_INSN_FUNCS(ldr_imm, 0x3FC00000, 0x39400000) __AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000) __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000) __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000) -__AARCH64_INSN_FUNCS(load_ex, 0x3F400000, 0x08400000) -__AARCH64_INSN_FUNCS(store_ex, 0x3F400000, 0x08000000) +__AARCH64_INSN_FUNCS(load_ex, 0x3FC00000, 0x08400000) +__AARCH64_INSN_FUNCS(store_ex, 0x3FC00000, 0x08000000) __AARCH64_INSN_FUNCS(mops, 0x3B200C00, 0x19000400) __AARCH64_INSN_FUNCS(stp, 0x7FC00000, 0x29000000) __AARCH64_INSN_FUNCS(ldp, 0x7FC00000, 0x29400000)