From patchwork Thu Feb 20 01:21:28 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peilin Ye X-Patchwork-Id: 13983160 X-Patchwork-Delegate: bpf@iogearbox.net Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0C081B4F17 for ; Thu, 20 Feb 2025 01:21:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740014494; cv=none; b=sq9jNFyWcaCLtq4jR7uKCfSlTNufymNOzfF/uyrTe0/VwWxcSZJVbKaNw1l+hQLJsvXLpAYPkeWq5pkUFZ2tZiHBVPhEu81ZC/3TEMklO80CtmIY8fhuAja8UbWpKR0mmFuzN0a0h94Fay2HpuCwTf3oWVDqonOFWbsI7nZk2dw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740014494; c=relaxed/simple; bh=gF7uoug7KIdG4iVdYIiLh1+x0bJcYmr2AWleOtXDkqo=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=R39So0nUqVcsFgiqjtCCR8/iO6HlWVPHCG8PeU9PcOfItl2fnXNEp8lgiV3OoJv1UShynRE3YGZas09jCbtnBywK+eDwsMOXjfh3ZwoYljWwOcTWb2TClaMb0t7sYKgtKMF+EB7w9uTr2OGuBFQk5y6914Ipk1G8LBTHUjgrDTc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--yepeilin.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=k9D3XmE5; arc=none smtp.client-ip=209.85.216.74 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--yepeilin.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="k9D3XmE5" Received: by mail-pj1-f74.google.com with SMTP id 98e67ed59e1d1-2f816a85facso1058575a91.3 for ; Wed, 19 Feb 2025 17:21:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1740014492; x=1740619292; darn=vger.kernel.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=OkZLa2X4XrqPLAsbeivrvq2/n6STf/0Lx6m+57nkDis=; b=k9D3XmE5Om1s6MteEcCvhchR6B808b3aGlt+zPdFuZRU2xhjlXR2rGRAcChUkBUpzM BKU2qq9ktXXecgPYv2e57UXMvaaUOr4z83J80VZUnhblkKEPbvKDGk1zVh18iCqa68Qk ohbw8efw4IB9rFNUtDqi/pklN6XL2C3fTiIDlgGAO3ozk1yEcSbbLDpNBMwelqU9MD3s cg0xZiaQ/p+gB7cKmeu69mnvAGJ/F+GA6VQyfJJvydl53BV/mxM4GO5GTW36Xxjrmol6 owE6zM1DNTh50oD//nbUHUIah2k833L/01STWPtgQPkf9Zc5a3A06nKGIhM3OKrEZaku YIkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740014492; x=1740619292; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=OkZLa2X4XrqPLAsbeivrvq2/n6STf/0Lx6m+57nkDis=; b=CCenUrZYP8uDMZlfv1AaIraUKcIO8JrgN8ln/v1MUAZWenCIXtLN68Q84CdrnP+yr6 ZxRx+ihbVycSlvYL2NGKmazUjWfs1gXrWFxOJPJw2yFVVAZUHMvcs/4lQhrarmbNB6yz ErPq6IcDdlgbOikiJowl5s+EYVws/UHlAJHe5IJOT7BoE62Otf0qqXXUZQfC7d3U+L2C VAf5gxBF4TwSIuiS/cAvRIyoBy4jcn3fVM/GP0zVhmyp+J4k6l1e2BQKfKycpPkPsPL1 Ar6/v0Vw7dpqSaGKXGGjA1rx9MtbaByHBStAxDmBbsdcSsh29yjRF8/Xy2nlWiUZqNEy Pmnw== X-Gm-Message-State: AOJu0Yz6GWn8HYvzZ0m5z3lsJ2MSEB+rYwOHU9WtK6/kPiRfxGEMev4q Ri7y9ZkUaCYUyTr3r1FVnDQyL4zjrWa0DDtjIOiGkm/4B3tG2iYAzv6DHqZTvSVt6cXYSxNqn6W sEG8zubWZ8OzUMG0PIDGCLiAu4jiMHetAfoU72RspNzt5yaA1MoDEdb1J4F+s+AuQEft89rMIpA CAJbP5O0POoa8ZA8XRqhlBWwyMGn1QfkEqOVHLXlg= X-Google-Smtp-Source: AGHT+IFBxisbnr8xuVdH6zyqBX5cRFTXzSlnuc/uizTOJqWix9sLLV310uViRu8QUCqCKsN5Tzuuv6azaPxpIg== X-Received: from pjbhl4.prod.google.com ([2002:a17:90b:1344:b0:2fa:a101:755]) (user=yepeilin job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:2d8d:b0:2ee:f076:20fb with SMTP id 98e67ed59e1d1-2fc40f22db2mr35640374a91.17.1740014492129; Wed, 19 Feb 2025 17:21:32 -0800 (PST) Date: Thu, 20 Feb 2025 01:21:28 +0000 In-Reply-To: Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: X-Mailer: git-send-email 2.48.1.601.g30ceb7b040-goog Message-ID: Subject: [PATCH bpf-next v3 6/9] arm64: insn: Add load-acquire and store-release instructions From: Peilin Ye To: bpf@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Peilin Ye , bpf@ietf.org, Xu Kuohai , Eduard Zingerman , David Vernet , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , Martin KaFai Lau , Song Liu , Yonghong Song , John Fastabend , KP Singh , Stanislav Fomichev , Hao Luo , Jiri Olsa , Jonathan Corbet , "Paul E. McKenney" , Puranjay Mohan , Ilya Leoshkevich , Heiko Carstens , Vasily Gorbik , Catalin Marinas , Will Deacon , Quentin Monnet , Mykola Lysenko , Shuah Khan , Ihor Solodrai , Yingchi Long , Josh Don , Barret Rhoden , Neel Natu , Benjamin Segall , linux-kernel@vger.kernel.org X-Patchwork-Delegate: bpf@iogearbox.net Add load-acquire ("load_acq", LDAR{,B,H}) and store-release ("store_rel", STLR{,B,H}) instructions. Breakdown of encoding: size L (Rs) o0 (Rt2) Rn Rt mask (0x3fdffc00): 00 111111 1 1 0 11111 1 11111 00000 00000 value, load_acq (0x08dffc00): 00 001000 1 1 0 11111 1 11111 00000 00000 value, store_rel (0x089ffc00): 00 001000 1 0 0 11111 1 11111 00000 00000 As suggested by Xu [1], include all Should-Be-One (SBO) bits ("Rs" and "Rt2" fields) in the "mask" and "value" numbers. It is worth noting that we are adding the "no offset" variant of STLR instead of the "pre-index" variant, which has a different encoding. Reference: Arm Architecture Reference Manual (ARM DDI 0487K.a, ID032224), * C6.2.161 LDAR * C6.2.353 STLR [1] https://lore.kernel.org/bpf/4e6641ce-3f1e-4251-8daf-4dd4b77d08c4@huaweicloud.com/ Signed-off-by: Peilin Ye Acked-by: Xu Kuohai --- arch/arm64/include/asm/insn.h | 8 ++++++++ arch/arm64/lib/insn.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index 2d8316b3abaf..39577f1d079a 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -188,8 +188,10 @@ enum aarch64_insn_ldst_type { AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX, AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX, AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX, + AARCH64_INSN_LDST_LOAD_ACQ, AARCH64_INSN_LDST_LOAD_EX, AARCH64_INSN_LDST_LOAD_ACQ_EX, + AARCH64_INSN_LDST_STORE_REL, AARCH64_INSN_LDST_STORE_EX, AARCH64_INSN_LDST_STORE_REL_EX, AARCH64_INSN_LDST_SIGNED_LOAD_IMM_OFFSET, @@ -351,6 +353,8 @@ __AARCH64_INSN_FUNCS(ldr_imm, 0x3FC00000, 0x39400000) __AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000) __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000) __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000) +__AARCH64_INSN_FUNCS(load_acq, 0x3FDFFC00, 0x08DFFC00) +__AARCH64_INSN_FUNCS(store_rel, 0x3FDFFC00, 0x089FFC00) __AARCH64_INSN_FUNCS(load_ex, 0x3FC00000, 0x08400000) __AARCH64_INSN_FUNCS(store_ex, 0x3FC00000, 0x08000000) __AARCH64_INSN_FUNCS(mops, 0x3B200C00, 0x19000400) @@ -602,6 +606,10 @@ u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1, int offset, enum aarch64_insn_variant variant, enum aarch64_insn_ldst_type type); +u32 aarch64_insn_gen_load_acq_store_rel(enum aarch64_insn_register reg, + enum aarch64_insn_register base, + enum aarch64_insn_size_type size, + enum aarch64_insn_ldst_type type); u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg, enum aarch64_insn_register base, enum aarch64_insn_register state, diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c index b008a9b46a7f..9bef696e2230 100644 --- a/arch/arm64/lib/insn.c +++ b/arch/arm64/lib/insn.c @@ -540,6 +540,35 @@ u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1, offset >> shift); } +u32 aarch64_insn_gen_load_acq_store_rel(enum aarch64_insn_register reg, + enum aarch64_insn_register base, + enum aarch64_insn_size_type size, + enum aarch64_insn_ldst_type type) +{ + u32 insn; + + switch (type) { + case AARCH64_INSN_LDST_LOAD_ACQ: + insn = aarch64_insn_get_load_acq_value(); + break; + case AARCH64_INSN_LDST_STORE_REL: + insn = aarch64_insn_get_store_rel_value(); + break; + default: + pr_err("%s: unknown load-acquire/store-release encoding %d\n", + __func__, type); + return AARCH64_BREAK_FAULT; + } + + insn = aarch64_insn_encode_ldst_size(size, insn); + + insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT, insn, + reg); + + return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, + base); +} + u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg, enum aarch64_insn_register base, enum aarch64_insn_register state,