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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , CC: Ido Schimmel , Amit Cohen , "Petr Machata" , Subject: [PATCH net-next 10/15] mlxsw: pci: Remove unused wait queue Date: Tue, 2 Apr 2024 15:54:23 +0200 Message-ID: X-Mailer: git-send-email 2.44.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CEB:EE_|CH3PR12MB9195:EE_ X-MS-Office365-Filtering-Correlation-Id: 511733d0-375d-43bb-3cd1-08dc531ce173 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 5k6eq66fbYhjU3pEMUZxF3EbomC/1abR2m4c1ULO14GJ6kSSSt6JyDcLUCCvfsJXmZuX9GJYdE9gZayCrHtUJ61wVBNoqSSJX65ZAiUIZLEW/5/m+fYjSeDb3nyFPri79Ah99WZaWYmUzxthgIUfczmGlUVpRQaCztEMjffnxS7bBnnaSzm02D0bEBVT14bQ+TsyaBsYKIM40Bm1BTsE9tHUAmHnYIEaNPRYpfkwAfa5/1rF4BGUAnlGmjMNgYsWmPg6mlast31B50OF1sXSNzk4AnRIA8hWdiwNUsVok+BNhdFteQnh12HFiMvgM8KSEZDFq1M0okty77Dm6vFyN0alV3BhZ+4Z+uCN64ipdjnRTmjMtckzYL0NhjzCKgUJ8M6p2GNvcxBgVLMShMCgkzMcKHb6IfUwzfrIh1gYeg4k/MuHLEQl0dExYS6arghQyTQpv4WQ8B+8BragVAr2UwOvUQ/0CNYgaYAozyTCZxfzzB8Y35NkX6rypE4xEGz+5AyFtmndn439MbdZ6+hOc+qKOe/BLBItvele1Dgt4huS08PogWIVk/9qpBu2FcE+FrnXUQ2HjXvQEx18kpSNg9OEUCvapa+tgr1y8y13qZ0wolMqyPmGZP/bhPlsIFEVUN4Ho960uidtRyVSX9ykhFl2qGdoNpOsARdtNIMOLeQ2uAyhseDBapssn63sNWWYxH+zODpmE9ME830LrjFYANYAyEmKmIRFXDVnMsozlHc5cb2YTPKkEbT+c4LI5Hsz X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(1800799015)(82310400014)(376005)(36860700004);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2024 13:57:48.6070 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 511733d0-375d-43bb-3cd1-08dc531ce173 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CEB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9195 X-Patchwork-Delegate: kuba@kernel.org From: Amit Cohen The previous patch changed the code to do not handle command interface from event queue. With this change the wait queue is not used anymore. Remove it and 'wait_done' variable. Signed-off-by: Amit Cohen Reviewed-by: Ido Schimmel Signed-off-by: Petr Machata Reviewed-by: Simon Horman --- drivers/net/ethernet/mellanox/mlxsw/pci.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlxsw/pci.c b/drivers/net/ethernet/mellanox/mlxsw/pci.c index 3460a4ef7d9a..7f059306af5a 100644 --- a/drivers/net/ethernet/mellanox/mlxsw/pci.c +++ b/drivers/net/ethernet/mellanox/mlxsw/pci.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -111,8 +110,6 @@ struct mlxsw_pci { struct mlxsw_pci_mem_item out_mbox; struct mlxsw_pci_mem_item in_mbox; struct mutex lock; /* Lock access to command registers */ - wait_queue_head_t wait; - bool wait_done; struct { u8 status; u64 out_param; @@ -1819,8 +1816,8 @@ static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, struct mlxsw_pci *mlxsw_pci = bus_priv; dma_addr_t in_mapaddr = 0, out_mapaddr = 0; unsigned long timeout = msecs_to_jiffies(MLXSW_PCI_CIR_TIMEOUT_MSECS); - bool *p_wait_done = &mlxsw_pci->cmd.wait_done; unsigned long end; + bool wait_done; int err; *p_status = MLXSW_CMD_STATUS_OK; @@ -1844,7 +1841,7 @@ static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, mlxsw_pci_write32(mlxsw_pci, CIR_IN_MODIFIER, in_mod); mlxsw_pci_write32(mlxsw_pci, CIR_TOKEN, 0); - *p_wait_done = false; + wait_done = false; wmb(); /* all needs to be written before we write control register */ mlxsw_pci_write32(mlxsw_pci, CIR_CTRL, @@ -1857,7 +1854,7 @@ static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, u32 ctrl = mlxsw_pci_read32(mlxsw_pci, CIR_CTRL); if (!(ctrl & MLXSW_PCI_CIR_CTRL_GO_BIT)) { - *p_wait_done = true; + wait_done = true; *p_status = ctrl >> MLXSW_PCI_CIR_CTRL_STATUS_SHIFT; break; } @@ -1865,7 +1862,7 @@ static int mlxsw_pci_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod, } while (time_before(jiffies, end)); err = 0; - if (*p_wait_done) { + if (wait_done) { if (*p_status) err = -EIO; } else { @@ -1963,7 +1960,6 @@ static int mlxsw_pci_cmd_init(struct mlxsw_pci *mlxsw_pci) int err; mutex_init(&mlxsw_pci->cmd.lock); - init_waitqueue_head(&mlxsw_pci->cmd.wait); err = mlxsw_pci_mbox_alloc(mlxsw_pci, &mlxsw_pci->cmd.in_mbox); if (err)